ad9361_adc_sub HDL Worker

Detail

The ad9361_adc_sub.hdl subdevice worker handles registering and de-interleaving of ADC data made available via the dev_data_from_pins devsignal port. This worker’s LVDS_p, HALF_DUPLEX_p, SINGLE_PORT_p, and DATA_RATE_CONFIG_p parameter properties allow for and enforce build-time configuration of the possible AD9361 RX data time-interleaved modes. The currently supported modes and their limitations are shown in the following table.

Table 103: Supported ADC Sampling Rates per RX channel

Platform/Cards which

AD9361 Data Port Mode

AD9361 Channel Mode

Max AD9361-

Max

allow the AD9361

Supported Sampling

ad9361_adc_sub.hdl-

Data Port/Channel

Rate per RX channel

Supported Sampling

Mode

Rate per RX channel

E310

CMOS Single Port Half Duplex SDR

not yet supported

E310

CMOS Single Port Half Duplex DDR

not yet supported

E310

CMOS Single Port Full Duplex SDR

not yet supported

E310

CMOS Single Port Full Duplex DDR

not yet supported

E310

CMOS Dual Port Half Duplex SDR

not yet supported

E310

CMOS Dual Port Half Duplex DDR

not yet supported

E310

CMOS Dual Port Full Duplex SDR

not yet supported

E310

CMOS Dual Port Full Duplex DDR

not yet supported

E310

CMOS Single Port Full Duplex DDR

1R1T, 2R2T Timing=0

30.72 Msps

30.72 Msps

E310

CMOS Single Port Full Duplex DDR

1R1T, 2R2T Timing=1, 2R1T, 1R2T

15.36 Msps

15.36 Msps

FMCOMMS2/3

LVDS (Dual Port Full Duplex DDR)

all configs

61.44 Msps

61.44 Msps (There are limited guarantees of data fidelity on the FMCOMMS2/3 cards for certain multichannel modes on certain platforms, although tests at room temperature have always yielded 100% fidelity. For more info see the maximum sample rate and BER tables.)

Data is sent out the dev_data_ch0_out and dev_data_ch1_out devsignal ports for channel 0 and channel 1, respectively. Note that channel 0 corresponds to the AD9361 R1 channel and channel 1 corresponds to the AD9361 R2 channel when the channels_are_swapped property has a value of false. The channel relationship is otherwise reversed. Note that which of the two AD9361 RX analog RF port’s signal is sent in the R1 and R2 time slots are variable depending on the AD9361 register configuration. This relationship is shown in the following table.

Table 104: Channel Connectivity (D.C. means Don’t Care.)

channels_are_swapped

ad9361_adc_sub.hdl devsignal channel

AD9361 timing diagram channel

AD9361 TX RF Port

AD9361 Register 0x010 Bit D4 [r1]

AD9361 Register 0x003 Bits [D7 D6] [r2]

AD9361 Register 0x004 Bits [D5 D0]

False

0

R1

RX1A_N

0

[D.C. 1]

000001

False

0

R1

RX1A_P

0

[D.C. 1]

000010

False

0

R1

RX1B_N

0

[D.C. 1]

000100

False

0

R1

RX1B_P

0

[D.C. 1]

001000

False

0

R1

RX1C_N

0

[D.C. 1]

010000

False

0

R1

RX1C_P

0

[D.C. 1]

100000

False

0

R1

RX1A_P/RX1A_N

0

[D.C. 1]

000011

False

0

R1

RX1B_P/RX1B_N

0

[D.C. 1]

001100

False

0

R1

RX1C_P/RX1C_N

0

[D.C. 1]

110000

False

0

R1

RX2A_N

1

[1 D.C.]

000001

False

0

R1

RX2A_P

1

[1 D.C.]

000010

False

0

R1

RX2B_N

1

[1 D.C.]

000100

False

0

R1

RX2B_P

1

[1 D.C.]

001000

False

0

R1

RX2C_N

1

[1 D.C.]

010000

False

0

R1

RX2C_P

1

[1 D.C.]

100000

False

0

R1

RX2A_P/RX2A_N

1

[1 D.C.]

000011

False

0

R1

RX2B_P/RX2B_N

1

[1 D.C.]

001100

False

0

R1

RX2C_P/RX2C_N

1

[1 D.C.]

110000

False

1

R2 [r3]

RX2A_N

0

[1 D.C.]

000001

False

1

R2 [r3]

RX2A_P

0

[1 D.C.]

000010

False

1

R2 [r3]

RX2B_N

0

[1 D.C.]

000100

False

1

R2 [r3]

RX2B_P

0

[1 D.C.]

001000

False

1

R2 [r3]

RX2C_N

0

[1 D.C.]

010000

False

1

R2 [r3]

RX2C_P

0

[1 D.C.]

100000

False

1

R2 [r3]

RX2A_P/RX2A_N

0

[1 D.C.]

000011

False

1

R2 [r3]

RX2B_P/RX2B_N

0

[1 D.C.]

001100

False

1

R2 [r3]

RX2C_P/RX2C_N

0

[1 D.C.]

110000

False

1

R2 [r3]

RX1A_N

1

[D.C. 1]

000001

False

1

R2 [r3]

RX1A_P

1

[D.C. 1]

000010

False

1

R2 [r3]

RX1B_N

1

[D.C. 1]

000100

False

1

R2 [r3]

RX1B_P

1

[D.C. 1]

001000

False

1

R2 [r3]

RX1C_N

1

[D.C. 1]

010000

False

1

R2 [r3]

RX1C_P

1

[D.C. 1]

100000

False

1

R2 [r3]

RX1A_P/RX1A_N

1

[D.C. 1]

000011

False

1

R2 [r3]

RX1B_P/RX1B_N

1

[D.C. 1]

001100

False

1

R2 [r3]

RX1C_P/RX1C_N

1

[D.C. 1]

110000

True

0

R2 [r3]

RX2A_N

0

[1 D.C.]

000001

True

0

R2 [r3]

RX2A_P

0

[1 D.C.]

000010

True

0

R2 [r3]

RX2B_N

0

[1 D.C.]

000100

True

0

R2 [r3]

RX2B_P

0

[1 D.C.]

001000

True

0

R2 [r3]

RX2C_N

0

[1 D.C.]

010000

True

0

R2 [r3]

RX2C_P

0

[1 D.C.]

100000

True

0

R2 [r3]

RX2A_P/RX2A_N

0

[1 D.C.]

000011

True

0

R2 [r3]

RX2B_P/RX2B_N

0

[1 D.C.]

001100

True

0

R2 [r3]

RX2C_P/RX2C_N

0

[1 D.C.]

110000

True

0

R2 [r3]

RX1A_N

1

[D.C. 1]

000001

True

0

R2 [r3]

RX1A_P

1

[D.C. 1]

000010

True

0

R2 [r3]

RX1B_N

1

[D.C. 1]

000100

True

0

R2 [r3]

RX1B_P

1

[D.C. 1]

001000

True

0

R2 [r3]

RX1C_N

1

[D.C. 1]

010000

True

0

R2 [r3]

RX1C_P

1

[D.C. 1]

100000

True

0

R2 [r3]

RX1A_P/RX1A_N

1

[D.C. 1]

000011

True

0

R2 [r3]

RX1B_P/RX1B_N

1

[D.C. 1]

001100

True

0

R2 [r3]

RX1C_P/RX1C_N

1

[D.C. 1]

110000

True

1

R1

RX1A_N

0

[D.C. 1]

000001

True

1

R1

RX1A_P

0

[D.C. 1]

000010

True

1

R1

RX1B_N

0

[D.C. 1]

000100

True

1

R1

RX1B_P

0

[D.C. 1]

001000

True

1

R1

RX1C_N

0

[D.C. 1]

010000

True

1

R1

RX1C_P

0

[D.C. 1]

100000

True

1

R1

RX1A_P/RX1A_N

0

[D.C. 1]

000011

True

1

R1

RX1B_P/RX1B_N

0

[D.C. 1]

001100

True

1

R1

RX1C_P/RX1C_N

0

[D.C. 1]

110000

True

1

R1

RX2A_N

1

[1 D.C.]

000001

True

1

R1

RX2A_P

1

[1 D.C.]

000010

True

1

R1

RX2B_N

1

[1 D.C.]

000100

True

1

R1

RX2B_P

1

[1 D.C.]

001000

True

1

R1

RX2C_N

1

[1 D.C.]

010000

True

1

R1

RX2C_P

1

[1 D.C.]

100000

True

1

R1

RX2A_P/RX2A_N

1

[1 D.C.]

000011

True

1

R1

RX2B_P/RX2B_N

1

[1 D.C.]

001100

True

1

R1

RX2C_P/RX2C_N

1

[1 D.C.]

110000
r1

Note that AD9361 register 0x010 Bit D4 is controlled by no-OS’s AD9361 InitParam struct’s rx channel swap enable member and that the ad9361 config proxy.rcc worker’s ad9361 init property sets that member value

r2

Note that AD9361 register 0x003 Bits [D7 D6] are controlled by no-OS’s AD9361 InitParam struct’s one rx one tx use rx num member and two rx two tx mode enable member and that the ad9361 config proxy.rcc worker’s ad9361 init property sets these member values

r3(1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36)

Note that data will only ever be de-interleaved for the R2 time slot and sent out the devsignal when the AD9361 register 0x010 bit D2 is 1 (which forces 2R2T timing) or when AD9361 register 0x003 Bits D7 and D6 are 1 (which corresponds to one of 2R1T or 2R2T mode)

Control Timing and Signals

Clock Domains

The AD9361 ADC SUB subdevice worker contains two clock domains: the clock from the Control Plane, and the AD9361 DATA_CLK_P clock from the dev_data_clk devsignal. The control clock domain is only used to read or write the channels_are_swapped, r1_samps_dropped, and r2_samps_dropped properties (all of which are synchronized between the clock domains in one direction or the other). The DATA_CLK_P domain is used for the registering/de-interleaving of RX data. The data sent out the dev_data_ch0_out and dev_data_ch1_out dev signals is on the DATA_CLK_P domain.

Latency

For the LVDS configuration or CMOS Single Port Full Duplex (DDR) configuration, the latency from the first active edge of the AD9361 DATA_CLK_P clock on which an R1 channel’s sample begins to the first rising edge of the output clock on the dev_data_ch0_out/dev_data_ch1_out port for the same sample is 6 DATA_CLK_P cycles. For these modes, the latency from the first active edge of the AD9361 DATA_CLK_P clock on which an R2 channel’s sample begins to the first rising edge of the output clock on the dev_data_ch0_out/dev_data_ch1_out port for the same sample is 4 DATA_CLK_P cycles.

Multichannel Phase Coherency

Note that the aforementioned 6 cycle/4 cycle latency results on the multichannel data being output the devsignal ports in a clock-aligned, phase coherent fashion. However, just because the each channel’s devsignal data is phase-aligned at the output of the ad9361_adc_sub.hdl worker’s devsignals, that does not mean that the data is phase-aligned once each channel is ingested inside an instance of an ad9361_adc.hdl device worker because each ad9361_adc.hdl instance handles its data as an independent, uniquely flow-controlled data path.

Worker Properties

  • LVDS_p

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • HALF_DUPLEX_p

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • SINGLE_PORT_p

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • DATA_RATE_CONFIG_p

    • Type: enum

      • Allowed values: ['SDR', 'DDR']

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • channels_are_swapped

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: false

  • r1_samps_dropped

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • r2_samps_dropped

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

Worker Ports

    Interfaces (other than data I/O ports):

  • dev_cfg_data

    • Type: devsignal

  • dev_cfg_data_rx

    • Type: devsignal

  • dev_data_clk

    • Type: devsignal

  • dev_data_from_pins

    • Type: devsignal

  • dev_data_ch0_out

    • Type: devsignal

  • dev_data_ch1_out

    • Type: devsignal

    • Subdevice Connections:

    • Supported device worker: ad9361_adc


      Connections:


      • Subdevice port: dev_adc

      • Supported worker port: dev_data_ch1_out

        • Index: None


Worker Signals

  • config_is_two_r

    • Direction: in

    • Differential: false

    • Pin: false

  • ch0_handler_is_present

    • Direction: out

    • Differential: false

    • Pin: false

  • ch1_handler_is_present

    • Direction: out

    • Differential: false

    • Pin: false

  • data_bus_index_direction

    • Direction: out

    • Differential: false

    • Pin: false

  • data_clk_is_inverted

    • Direction: out

    • Differential: false

    • Pin: false

  • islvds

    • Direction: out

    • Differential: false

    • Pin: false

  • isdualport

    • Direction: out

    • Differential: false

    • Pin: false

  • isfullduplex

    • Direction: out

    • Differential: false

    • Pin: false

  • isDDR

    • Direction: out

    • Differential: false

    • Pin: false

  • present

    • Direction: out

    • Differential: false

    • Pin: false

  • rx_frame_usage

    • Direction: out

    • Differential: false

    • Pin: false

  • rx_frame_is_inverted

    • Direction: out

    • Differential: false

    • Pin: false

  • DATA_CLK_P

    • Direction: in

    • Differential: false

    • Pin: false

  • data

    • Direction: in

    • Width: 24

    • Differential: false

    • Pin: false

  • rx_frame

    • Direction: in

    • Differential: false

    • Pin: false

  • adc_data_I

    • Direction: in

    • Width: 12

    • Differential: false

    • Pin: false

  • adc_data_Q

    • Direction: in

    • Width: 12

    • Differential: false

    • Pin: false

  • adc_clk

    • Direction: in

    • Differential: false

    • Pin: false

  • adc_give

    • Direction: in

    • Differential: false

    • Pin: false

Utilization

FPGA resource utilization, Fmax, and the theoretical bitstream clock / sample-rate limitations for ad9361_adc_sub are documented in Performance and Resource Utilization.

References