Ad9361 adc sub (ad9361_adc_sub)
Design
The AD9361 ADC SUB is a subdevice worker whose primary purpose is to de-interleave the AD9361 IC pin-provided time-interleaved RX data streams (independent of which of the IC’s P0/P1 buses the RX data stream came from). De-interleaving occurs according to the timing diagrams specified in the AD9361 Reference Manual. This worker ingests RX data from devsignals from Ad9361 data sub (ad9361_data_sub), de-interleaves it into at most two 12-bit (Q0.11) RX channel data buses, and makes each channel bus available to an instance of the supported ad9361_adc.hdl device worker via a devsignal port.
A block diagram representation of the implementation is given in Figure 180:
Figure 180: ad9361_adc_sub block diagram.
Interface
<HdlDevice language="vhdl" libraries='ocpi.core.bsv util'
OnlyTargets="zynq zynq_ise virtex6 isim xsim"
ExactParts="
zynq:xc7z020-1-clg484
zynq_ise:xc7z020_ise_alias-1-clg484
zynq_ultra:xczu7ev-2-ffvc1156e
virtex6:xc6vlx240t-1-ff1156
stratix4:ep4sgx230k-c2-f40
artix7:xc7a50t-2-csg325">
<!-- By design, this worker provides control and/or data plane functionality
that is never intended to be exposed by any other worker. Accordingly,
this worker defines the ComponentSpec element inside this OWD file, as
opposed to creating an OCS file including said functionality which could
be used by other workers. -->
<ComponentSpec/>
<!-- Parameters -->
<!-- This parameter property corresponds to the "LVDS Mode" bit 4 in the parallel port configuration 3
register at 0x012. -->
<Property name='LVDS_p' type='bool' parameter='true' default='false'
description='Use LVDS RX data bus de-interleaving scheme, otherwise use CMOS de-interleaving scheme.
Default is CMOS.'/>
<!-- This parameter property corresponds to the "Half Duplex Mode" bit 3 in the parallel port
configuration 3 register 0x12 -->
<Property name='HALF_DUPLEX_p' type='bool' parameter='true' default='false'
description='Use half duplex mode, otherwise use full duplex mode. Must be false when using LVDS mode.'/> <!-- TODO / FIXME support runtime_dynamic enumeration? -->
<!-- This parameter property corresponds to the "Single Port Mode" bit 2 in the parallel port
configuration 3 register 0x12 -->
<Property name='SINGLE_PORT_p' type='bool' parameter='true' default='false'
description='Use single port, otherwise use both (dual) ports. Default is to use both ports. Must be false when using LVDS mode.'/>
<!-- This parameter property corresponds to the "Single Data Rate" bit 5 in the parallel port
configuration 3 register 0x12 -->
<Property name='DATA_RATE_CONFIG_p' type='enum' enums='SDR,DDR'
parameter='true'
default='DDR'
description='This should have a value of DDR when LVDS_p has a value of true. Either value is acceptable when LVDS_p has a value of false (i.e. CMOS mode is used).'/>
<!-- Properties -->
<Property name='channels_are_swapped' type='bool' writable='1' default='false' description="This property exists not as a necessity driven from AD9361 functionality which must be accounted for, but rather as a convenient option to allow control of the routing between the AD9361 pin interface channels (R1 or R2 in the timing diagrams) and this worker's devsignal channels (0 or 1). When this property has a value of true, R1 is routed to channel 0 and R2 to channel 1. When false, the channel relationships are swapped."/>
<Property name='r1_samps_dropped' type='bool' volatile='1' writable='1' description="A value of true indicates that one or more samples were sent from AD9361 for its R1 channel (see UG-570 timing diagrams) at a moment in time where no ad9361_adc.hdl worker was assigned to ingest them. A value of true is only possible when an assembly is built with only one ad9361_adc.hdl worker and when this worker's channels_are_swapped property has a value of true, together which is an erroneous condition which should be avoided. The purpose of this property is to be an error check for the aforementioned erroneous condition. Writing a value of false will force the value to false. Writing a value of true will do nothing."/>
<Property name='r2_samps_dropped' type='bool' volatile='1' writable='1' description="A value of true indicates that one or more samples were sent from AD9361 for its R2 channel (see UG-570 timing diagrams) at a moment in time where no ad9361_adc.hdl worker was assigned to ingest them. A value of true is possible, for example, when when an assembly is built with only one ad9361_adc.hdl worker and the AD9361 is configured for multichannel mode (2X2), together which is an erroneous condition which should be avoided. The purpose of this property is to be an error check for the aforementioned erroneous condition. Writing a value of false will force the value to false. Writing a value of true will do nothing."/>
<!-- Dev Signal Ports -->
<devsignal name='dev_cfg_data' signals='ad9361-cfg-data-signals.xml' master='true'/>
<devsignal name='dev_cfg_data_rx' signals='ad9361-cfg-data-rx-signals.xml' master='true'/>
<devsignal name='dev_data_clk' signals='ad9361-data-clk-signals.xml' master='true'/>
<devsignal name='dev_data_from_pins' signals='ad9361-data-adc-signals.xml' master='true'/>
<devsignal name='dev_data_ch0_out' signals='adc-12-signals.xml'/>
<devsignal name='dev_data_ch1_out' optional='true' signals='adc-12-signals.xml'/>
<!-- Sub-Device Port Connections (Supports) -->
<supports worker='ad9361_adc'>
<connect port="dev_adc" to="dev_data_ch0_out"/>
</supports>
<supports worker='ad9361_adc'>
<connect port="dev_adc" to="dev_data_ch1_out"/>
</supports>
</HdlDevice>
Implementations
ad9361_adc_sub(HDL)
Dependencies
The dependencies to other elements in OpenCPI are:
assets/hdl/devices/ad9361_adc_sub.hdl/ad9361_adc_sub.vhd
core/hdl/primitives/util/util_pkg.vhd
core/hdl/primitives/util/sync_status.vhd
core/hdl/primitives/bsv/imports/SyncBit.v
core/hdl/primitives/bsv/imports/SyncResetA.v
core/hdl/primitives/bsv/imports/SyncHandshake.v
core/hdl/primitives/bsv/bsv_pkg.vhd
Limitations
Limitations of ad9361_adc_sub are:
None.
Testing
Tested platforms include Agilent Zedboard/Analog Devices FMCOMMS2 (Vivado only), Agilent Zedboard/Analog Devices FMCOMMS3 (Vivado only), Ettus E310 (Vivado only, application for testing exists in e310 project).
No unit test for this component exists. However, a hardware-in-the-loop application (which is NOT a unit test) exists for testing purposes (see assets/applications/ad9361_adc_test).
Appendix
Vivado timing analysis details for ad9361_adc_sub are documented in Appendix.