Performance and Resource Utilization
The FPGA resource utilization and Fmax are included for this worker. Fmax refers to the maximum allowable clock rate for any registered signal paths within a given clock domain for an FPGA design. Fmax in the table below is specific only to this worker and represents the maximum possible Fmax for any OpenCPI bitstream built with this worker included. Note that the Fmax value for a given clock domain for the final bitstream is often worse than the Fmax specific to this worker, even if this worker is the only one included in the bitstream. It’s important to note that the full range of possible operating conditions for the AD9361 is not guaranteed to operate without error, e.g. maximum achievable RX sample rates in certain LVDS modes are less than AD9361 LVDS mode-maximum of 245.76 MHz. For more information, see Tables Table 106:, Table 107:, and Table 108:.
In the tables below, dev_data_clk is the worker source code name for the signal which is ultimately driven by, and has the same clock rate of, the AD9361 DATA_CLK pin pair.
Configuration |
OCPI Target |
Tool |
Version |
Device |
Registers (Typ) |
LUTs (Typ) |
Fmax (MHz) (Typ): control plane clock / dev_adc.adc_clk clock |
Memory/Special Functions |
|
0 |
zynq |
Vivado |
2017.1 |
xc7z020clg484-1 |
175 |
87 |
BUFR: 1 |
||
0 |
virtex6 |
ISE |
14.7 |
6vlx240tff1156-1 |
155 |
163 |
437.445 / |
BUFR: 1 |
|
1 |
zynq |
Vivado |
2017.1 |
xc7z020clg484-1 |
175 |
87 |
N/A |
||
1 |
virtex6 |
ISE |
14.7 |
6vlx240tff1156-1 |
155 |
163 |
437.445 / |
N/A |
A notable example of the aforementioned potential discrepancy between worker Fmax and bitstream Fmax for a given clock domain is the maximum achievable AD9361 LVDS RX data clock rate for Zynq 7020 speed grade 1 bitstreams containing this worker. The bitstream Fmax in this case is significantly lower than the worker netlist Fmax of 418 MHz on a Zynq 7020 speed grade 1. The timing analysis for the ad9361_adc_sub netlist is not capable of taking into account the paths from the internal-to-the-AD9361 registers which produce the RX data to the ad9361_adc_sub worker’s DDR register inputs. The Fmax discrepancy in this case results from these external-to-the-ad9361_adc_sub paths being the limiting factor for the max bistream RX data clock rate. In order to perform a timing analysis which does include these paths, and therefore takes into account all paths which may limit the maximum achievable RX data clock rate, a timing analysis must be done 1) on a netlist/bitstream which includes the rest of the path from the DDR input from the FPGA pad (i.e. it includes the ad9361_data_sub worker) and 2) which includes delay/offset constraints which contain the information about the range of possible clock/data skews from the internal-to-the-AD9361 register which produced the RX data to the FPGA pad (i.e. constraints are used which include the AD9361 datasheet-specified \(t_{DDRX}\) and \(t_{DDVV}\) min/max values).
Table Table 106: includes the known theoretical limitations at the bitstream level (as opposed to ad9361_adc_sub level) for the AD9361 DATA_CLK clock rate for various hardware/software configurations. For convenience, Table Table 107: converts the AD9361 DATA_CLK rate limitations into their consequential RX sample rate limitations. Table Table 108: contains the experimental verification results for RX sample rate limitations.
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
Notes |
min dev_data_clk (AD9361 DATA_CLK) clock period |
Zedboard w/ FMC voltage 2.5V, FMCOMMS2/3; Vivado 2017.1 Design Suite; AD9361 DATA_CLK duty cycle=50% 2; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0 |
5.712 3 |
5.712 3 |
ns |
(approx 175.070028011 MHz), guaranteed by FPGA timing analysis |
|
min dev_data_clk (AD9361 DATA_CLK) clock period |
Zedboard w/ FMC voltage 2.5V, FMCOMMS2/3; ISE 14.7 Design Suite; AD9361 DATA_CLK duty cycle=50% 2; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=3, AD9361 Rx Data Delay=0, AD9361 \(t_{DDRX}=0.75 ns\) 2, AD9361 \(t_{DDVV}=0.75 ns\) 2 |
4.294 3 |
4.294 3 |
ns |
(approx 232.883092687 MHz), guaranteed by FPGA timing analysis |
|
min dev_data_clk (AD9361 DATA_CLK) clock period |
ML605, one FMCOMMS2/3 in either slot; ISE 14.7 Design Suite; AD9361 DATA_CLK duty cycle=50% 2; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0, AD9361 \(t_{DDRX}=0.75 ns\) 2, AD9361 \(t_{DDVV}=0.75 ns\) 2 |
3.545 |
ns |
(approx 282 MHz), guaranteed by FPGA timing analysis |
||
min dev_data_clk (AD9361 DATA_CLK) clock period |
Ettus E310; Vivado 2017.1 Design Suite; AD9361 DATA_CLK duty cycle=50% 2; AD9361 LVDS Mode=0; AD9361 Half Duplex Mode=0; AD9361 Single Port Mode=1; AD9361 Single Data Rate=0; AD9361 DATA_CLK Delay=11, AD9361 Rx Data Delay=0 |
16.276 |
16.276 |
ns |
(approx 61.44 MHz), guaranteed by FPGA timing analysis |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
Notes |
bitstream minimum supported RX sample period for a given AD9361 antenna port / channel |
Zedboard w/ FMC voltage jumper setting 2.5V, FMCOMMS2/3; Vivado 2017.1 Design Suite bitstream; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 0; full range of FPGA voltages/temperatures, AD9361 DATA_CLK duty cycle=50% 2 |
11.424 |
11.424 |
ns |
(approx 87.535014005 Msps complex per RX channel), guaranteed by FPGA timing analysis |
|
bitstream minimum supported RX sample period for a given AD9361 antenna port / channel |
Zedboard w/ FMC voltage jumper setting 2.5V, FMCOMMS2/3; Vivado 2017.1 Design Suite bitstream; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0; AD9361 2R1T mode or 2R2T mode or AD9361 2R2T Timing = 1; full range of FPGA voltages/temperatures, AD9361 DATA_CLK duty cycle=50% 2 |
22.848 4 |
22.848 4 |
ns |
(approx 43.767507002 Msps complex 4 per RX channel), guaranteed by FPGA timing analysis |
|
bitstream minimum supported RX sample period for a given AD9361 antenna port / channel |
Zedboard w/ FMC voltage jumper setting 2.5V, FMCOMMS2/3; ISE 14.7 Design Suite bitstream; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=3, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 0; full range of FPGA voltages/temperatures, AD9361 DATA_CLK duty cycle=50% 2, AD9361 \(t_{DDRX}=0.75 ns\) 2, AD9361 \(t_{DDVV}=0.75 ns\) 2 |
8.588 |
8.588 |
ns |
(approx 116.441546343 Msps complex per RX channel), guaranteed by FPGA timing analysis |
|
bitstream minimum supported RX sample period for a given AD9361 antenna port / channel |
Zedboard w/ FMC voltage jumper setting 2.5V, FMCOMMS2/3; ISE 14.7 Design Suite bitstream; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=3, AD9361 Rx Data Delay=0; AD9361 2R1T mode or 2R2T mode or AD9361 2R2T Timing = 1; full range of FPGA voltages/temperatures, AD9361 DATA_CLK duty cycle=50% 2, AD9361 \(t_{DDRX}=0.75 ns\) 2, AD9361 \(t_{DDVV}=0.75 ns\) 2 |
17.176 4 |
17.176 4 |
ns |
(approx 58.220773171 Msps complex 4 per RX channel), guaranteed by FPGA timing anaylysis |
|
bitstream minimum supported RX sample period for a given AD9361 antenna port / channel |
ML605, one FMCOMMS2/3 in either slot; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 0; full range of FPGA voltages/temperatures, AD9361 DATA_CLK duty cycle=50% 2, AD9361 \(t_{DDRX}=0.75 ns\) 2, AD9361 \(t_{DDVV}=0.75 ns\) 2 |
7.090 |
ns |
(approx 141.043723554 Msps complex per RX channel), guaranteed by FPGA timing anaylysis |
||
bitstream minimum supported RX sample period for a given AD9361 antenna port / channel |
ML605, one FMCOMMS2/3 in either slot; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0; AD9361 2R1T mode or 2R2T mode or AD9361 2R2T Timing = 1; full range of FPGA voltages/temperatures, AD9361 DATA_CLK duty cycle=50% 2, AD9361 \(t_{DDRX}=0.75 ns\) 2, AD9361 \(t_{DDVV}=0.75 ns\) 2 |
14.180 |
ns |
(approx 70.521861777 Msps complex per RX channel), guaranteed by FPGA timing anaylysis |
||
bitstream minimum supported RX sample period for a given AD9361 antenna port / channel |
Ettus E310; Vivado 2017.1 Design Suite bitstream; AD9361 LVDS Mode=0; AD9361 Half Duplex Mode=0; AD9361 Single Port Mode=1; AD9361 Single Data Rate=0; AD9361 DATA_CLK Delay=11, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 0; full range of FPGA voltages/temperatures, AD9361 DATA_CLK duty cycle=50% 2 |
32.552 |
ns |
(approx 30.72 Msps complex per RX channel), guaranteed by FPGA timing anaylysis |
||
bitstream minimum supported RX sample period for a given AD9361 antenna port / channel |
Ettus E310; Vivado 2017.1 Design Suite bitstream; AD9361 LVDS Mode=0; AD9361 Half Duplex Mode=0; AD9361 Single Port Mode=1; AD9361 Single Data Rate=0; AD9361 DATA_CLK Delay=11, AD9361 Rx Data Delay=0; AD9361 2R1T mode or 2R2T mode or AD9361 2R2T Timing = 1; full range of FPGA voltages/temperatures, AD9361 DATA_CLK duty cycle=50% 2 |
65.104 |
ns |
(approx 15.36 Msps complex per RX channel), guaranteed by FPGA timing anaylysis |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
Notes |
RX bit error rate |
Zedboard w/ FMC voltage jumper setting 2.5V, FMCOMMS2/3; Vivado 2017.1 Design Suite bitstream; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 0; room temperature, RX sample rate=61.44 Msps complex (approx, nominal) |
0 |
0 |
% |
AD9361 PRBS test |
|
RX bit error rate |
Zedboard w/ FMC voltage jumper setting 2.5V, FMCOMMS2/3; Vivado 2017.1 Design Suite bitstream; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 1; room temperature, RX sample rate=43.767507 Msps complex 5 (approx, nominal) |
0 |
0 |
% |
||
RX bit error rate |
Zedboard w/ FMC voltage jumper setting 2.5V, FMCOMMS2/3; ISE 14.7 Design Suite bitstream; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=3, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 0; room temperature, RX sample rate=61.44 Msps complex (approx, nominal) |
0 |
0 |
% |
||
RX bit error rate |
Zedboard w/ FMC voltage jumper setting 2.5V, FMCOMMS2/3; ISE 14.7 Design Suite bitstream; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=3, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 1; room temperature, RX sample rate=58.220773 Msps complex 5 (approx, nominal) |
0 |
0 |
% |
||
RX bit error rate |
ML605 in CentOS7 x86 machine PCIe slot, one FMCOMMS2/3 in either slot; AD9361 LVDS Mode=1; AD9361 DATA_CLK Delay=2, AD9361 Rx Data Delay=0; AD9361 1R1T mode; room temperature, RX sample rate=61.44 Msps complex (approx, nominal) |
0 |
0 |
% |
||
RX bit error rate |
Ettus E310; Vivado 2017.1 Design Suite bitstream; AD9361 LVDS Mode=0; AD9361 Half Duplex Mode=0; AD9361 Single Port Mode=1; AD9361 Single Data Rate=0; AD9361 DATA_CLK Delay=11, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 0; room temperature, RX sample rate=30.72 Msps complex (approx, nominal) |
0 |
0 |
% |
||
RX bit error rate |
Ettus E310; Vivado 2017.1 Design Suite bitstream; AD9361 LVDS Mode=0; AD9361 Half Duplex Mode=0; AD9361 Single Port Mode=1; AD9361 Single Data Rate=0; AD9361 DATA_CLK Delay=11, AD9361 Rx Data Delay=0; AD9361 1R1T mode, AD9361 2R2T Timing = 1; room temperature, RX sample rate=15.36 Msps complex (approx, nominal) |
0 |
0 |
% |
Footnotes
- 1(1,2,3,4)
These measurements were the result of a Vivado timing analysis which was different from the Vivado analysis performed by default for OpenCPI worker builds. For more info see Appendix.
- 2(1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24)
Note that a) this condition is driven by the limitations of the capabilities of Xilinx ISE/Vivado constraints, and b) the range of value(s) for this condition does not cover the full range of possible values for AD9361 for the given mode.
- 3(1,2,3,4)
Note this is more than the minimum AD9361 LVDS DATA_CLK Clock Period of 4.069 ns, i.e. not all possible AD9361 LVDS clock rates can be accounted for.
- 4(1,2,3,4,5,6)
Note this value corresponds to less than the maximum possible AD9361 sample rate per AD9361 antenna port/channel for the given mode.
- 5(1,2)
Note this value corresponds to less than the maximum possible AD9361 sample rate per AD9361 antenna port/channel for the given mode.