Ad9361 config proxy (`ad9361_config_proxy`)

Design

The AD9361 Config Proxy device worker proxy is a software wrapper for Analog Device’s No-OS software library. No-OS provides command and control of the AD9361 IC via a high-level API which ultimately controls SPI writes to the AD9361 register set. In order to provide functionality analogous to the No-OS API, this worker provides a one-to-one mapping between the No-OS function calls and worker properties.

A block diagram representation of the implementation is given in Figure 175:

Figure 175: ad9361_config_proxy block diagram.

Interface

<!-- OCS for AD9361 device control (ad9361_config.hdl) via ADI's no-OS software
     (see ad9361/sw/ad9361_api.h from 
     https://github.com/analogdevicesinc/no-os.git). This OCS essentially provides
     a one-to-one mapping between component properties and the no-OS API function
     calls. Everything herein is specific to the no-os.git commit ID
     e99393f2ba7f244c8328393e5d13d20e54a24419 (which was the latest commit from
     the 2016_R2 branch at the time of writing this OWD) -->
<componentspec>

  <!--********  WORKER-SPECIFIC PARAMETERS (independent of libad9361)     ********-->

  <property name='rx_nchannels'          parameter='1'   type='uchar'   default='2'/>
  <property name='tx_nchannels'          parameter='1'   type='uchar'   default='2'/>

  <!--******** PARAMETERS MATCHING MACROS/ENUMS IN LIBAD9361 HEADER FILES ********-->

  <!-- macros in ad9361_api.h - applies to the ..._en_dis property values         -->
  <property name='ENABLE'                parameter='1'   type='uchar'   default='1'/>
  <property name='DISABLE'               parameter='1'   type='uchar'   default='0'/>

  <!-- macros in ad9361_api.h - used for rf_port_input                            -->
  <property name='A_BALANCED'            parameter='1'   type='ulong'   default='0'/>
  <property name='B_BALANCED'            parameter='1'   type='ulong'   default='1'/>
  <property name='C_BALANCED'            parameter='1'   type='ulong'   default='2'/>
  <property name='A_N'                   parameter='1'   type='ulong'   default='3'/>
  <property name='A_P'                   parameter='1'   type='ulong'   default='4'/>
  <property name='B_N'                   parameter='1'   type='ulong'   default='5'/>
  <property name='B_P'                   parameter='1'   type='ulong'   default='6'/>
  <property name='C_N'                   parameter='1'   type='ulong'   default='7'/>
  <property name='C_P'                   parameter='1'   type='ulong'   default='8'/>
  <property name='TX_MON1'               parameter='1'   type='ulong'   default='9'/>
  <property name='TX_MON2'               parameter='1'   type='ulong'   default='10'/>
  <property name='TX_MON1_2'             parameter='1'   type='ulong'   default='11'/>

  <!-- macros in ad9361_api.h - used for tx_rf_port_output                        -->
  <property name='TXA'                   parameter='1'   type='ulong'   default='0'/>
  <property name='TXB'                   parameter='1'   type='ulong'   default='1'/>

  <!-- en_state_machine_mode                                                      -->
  <property name='ENSM_MODE_TX'          parameter='1'   type='long'    default='0'/>
  <property name='ENSM_MODE_RX'          parameter='1'   type='long'    default='1'/>
  <property name='ENSM_MODE_ALERT'       parameter='1'   type='long'    default='2'/>
  <property name='ENSM_MODE_FDD'         parameter='1'   type='long'    default='3'/>
  <property name='ENSM_MODE_WAIT'        parameter='1'   type='long'    default='4'/>
  <property name='ENSM_MODE_SLEEP'       parameter='1'   type='long'    default='5'/>
  <property name='ENSM_MODE_PINCTRL'     parameter='1'   type='long'    default='6'/>
  <property name='ENSM_MODE_PINCTRL_FDD_INDEP' parameter='1' type='long' default='7'/>

  <!-- rx_lo_int_ext and tx_lo_int_ext                                            -->
  <property name='INT_LO'                parameter='1'   type='uchar'   default='0'/>
  <property name='EXT_LO'                parameter='1'   type='uchar'   default='1'/>

  <!-- rx_gain_control_mode                                                       -->
  <property name='RF_GAIN_MGC'           parameter='1'   type='uchar'   default='0'/>
  <property name='RF_GAIN_FASTATTACK_AGC' parameter='1'  type='uchar'   default='1'/>
  <property name='RF_GAIN_SLOWATTACK_AGC' parameter='1'  type='uchar'   default='2'/>
  <property name='RF_GAIN_HYBRID_AGC'    parameter='1'   type='uchar'   default='3'/>

  <!-- ad9361.h's fir_dest enum (applies to set rx_fir_config.rx and set tx_fir_config.tx -->
  <property name='FIR_TX1'               parameter='1'   type='uchar'   default='0x01'/>
  <property name='FIR_TX2'               parameter='1'   type='uchar'   default='0x02'/>
  <property name='FIR_TX1_TX2'           parameter='1'   type='uchar'   default='0x03'/>
  <property name='FIR_RX1'               parameter='1'   type='uchar'   default='0x81'/>
  <property name='FIR_RX2'               parameter='1'   type='uchar'   default='0x82'/>
  <property name='FIR_RX1_RX2'           parameter='1'   type='uchar'   default='0x83'/>
  <property name='FIR_IS_RX'             parameter='1'   type='uchar'   default='0x80'/>

  <!-- ad9361.h definitions (applies to one_rx_one_tx_mode_use_... values)        -->
  <property name='RX_1'                  parameter='1'   type='uchar'   default='1'/>
  <property name='RX_2'                  parameter='1'   type='uchar'   default='2'/>
  <property name='TX_1'                  parameter='1'   type='uchar'   default='1'/>
  <property name='TX_2'                  parameter='1'   type='uchar'   default='2'/>

  <!-- ad9361.h's ad9361_pdata_rx_freq enum (applies to ...trx_path_clks property's array indices) -->
  <property name='BPLL_FREQ'             parameter='1'   type='uchar'   default='0'/>
  <property name='ADC_FREQ'              parameter='1'   type='uchar'   default='1'/>
  <property name='R2_FREQ'               parameter='1'   type='uchar'   default='2'/>
  <property name='R1_FREQ'               parameter='1'   type='uchar'   default='3'/>
  <property name='CLKRF_FREQ'            parameter='1'   type='uchar'   default='4'/>
  <property name='RX_SAMPL_FREQ'         parameter='1'   type='uchar'   default='5'/>
  <property name='NUM_RX_CLOCKS'         parameter='1'   type='uchar'   default='6'/>

  <!-- ad9361.h's ad9361_pdata_tx_freq enum (applies to ...trx_path_clks property's array indices) -->
  <property name='IGNORE'                parameter='1'   type='uchar'   default='0'/>
  <property name='DAC_FREQ'              parameter='1'   type='uchar'   default='1'/>
  <property name='T2_FREQ'               parameter='1'   type='uchar'   default='2'/>
  <property name='T1_FREQ'               parameter='1'   type='uchar'   default='3'/>
  <property name='CLKTF_FREQ'            parameter='1'   type='uchar'   default='4'/>
  <property name='TX_SAMPL_FREQ'         parameter='1'   type='uchar'   default='5'/>
  <property name='NUM_TX_CLOCKS'         parameter='1'   type='uchar'   default='6'/>

  <!-- enums in ad9361.h (applies to bist_tone mode value and bist_prbs value)                     -->
  <property name='BIST_DISABLE'          parameter='1'   type='ulong'   default='0'/>
  <property name='BIST_INJ_TX'           parameter='1'   type='ulong'   default='1'/> <!-- not recommended for use with bist_prbs -->
  <property name='BIST_INJ_RX'           parameter='1'   type='ulong'   default='2'/>

  <!-- macros in ad9361_api.h (applies to no_ch_mode property value)              -->
  <property name='MODE_1x1'              parameter='1'   type='uchar'   default='1'/>
  <property name='MODE_2x2'              parameter='1'   type='uchar'   default='2'/>

  <!-- macros in ad9361_api.h (applies to trx_fir_rate_gov property value         -->
  <property name='HIGHEST_OSR'           parameter='1'   type='ulong'   default='0'/>
  <property name='NOMINAL_OSR'           parameter='1'   type='ulong'   default='1'/>

  <!--**** PROPERTIES CORRESPONDING TO libad9361 "STANDARD" API (ad9361_api.h)****-->

  <property name='ad9361_rf_phy' type='struct'    volatile='1' description=''>
    <member name='clk_refin'                            type='struct'>
      <member name='rate'                               type='ulong'/>
    </member>
    <member name='pdata'                                type='struct'>
      <member name='rx2tx2'                             type='bool' description='When this value is false, the read values from the second index of following properties should be ignored: rx_gain_control_mode, rx_fir_config_read, tx_fir_config_read, and tx_rssi. When this value is false, the written values to the second index of the following properties will not be applied: rx_rf_gain, rx_gain_control_mode, and tx_attenuation.'/>
      <member name='fdd'                                type='bool'/>
      <member name='use_extclk'                         type='bool'/>
      <member name='dcxo_coarse'                        type='ulong'/>
      <member name='dcxo_fine'                          type='ulong'/>
      <member name='rx1tx1_mode_use_rx_num'             type='ulong'/>
      <member name='rx1tx1_mode_use_tx_num'             type='ulong'/>
    </member>
  </property>

  <property name='ad9361_init' type='struct'                 initial='1'  default='reference_clk_rate 40e6,one_rx_one_tx_mode_use_rx_num 1,one_rx_one_tx_mode_use_tx_num 1,frequency_division_duplex_mode_enable 1,xo_disable_use_ext_refclk_enable 0,two_t_two_r_timing_enable 0,pp_tx_swap_enable 1,pp_rx_swap_enable 1,tx_channel_swap_enable 1,rx_channel_swap_enable 1,delay_rx_data 0,rx_data_clock_delay 0,rx_data_delay 4,tx_fb_clock_delay 7,tx_data_delay 0' description='Initialize the AD9361 part.'>
    <member name='reference_clk_rate'                    type='ulong'/>
    <member name='one_rx_one_tx_mode_use_rx_num'         type='uchar' description='Set to RX_1 or RX_2 to set desired channel in 1x1 mode. For example, When set to RX_2 mode, the R1 and R2 data paths in the timing diagrams will be swapped.'/>
    <member name='one_rx_one_tx_mode_use_tx_num'         type='uchar' description='Set to TX_1 or TX_2 to set desired channel in 1x1 mode. For example, When set to TX_2 mode, the T1 and T2 data paths in the timing diagrams will be swapped.'/>
    <member name='frequency_division_duplex_mode_enable' type='uchar' description='Acceptable values are 1 for true and 0 for false.'/>
    <member name='xo_disable_use_ext_refclk_enable'      type='uchar'/>
    <member name='two_t_two_r_timing_enable'             type='bool' description='Setting to true forces 2R2T timing regardless of number of enabled RX/TX channels. Recommended to set to false if only using at most one RX or one TX channel for the duration of an application (this will lower needed DATA_CLK_P rate). Setting to true has the advantage of ensuring that the timing diagram for each of the RX and TX data paths will not change when dynamically enabling/disabling any of the 4 possible channels (2 RX, 2 TX) at runtime - this comes at the cost of a higher required DATA_CLK_P rate).'/>
    <member name='pp_tx_swap_enable'                     type='uchar' description='Setting to 1 swaps I and Q (performs spectral inversion). Setting to 0 does not swap.'/>
    <member name='pp_rx_swap_enable'                     type='uchar' description='Setting to 1 swaps I and Q (performs spectral inversion). Setting to 0 does not swap.'/>
    <member name='tx_channel_swap_enable'                type='uchar' description='Setting to 1 swaps RX channels 0 and 1. Setting to 0 does not swap.'/>
    <member name='rx_channel_swap_enable'                type='uchar' description='Setting to 1 swaps RX channels 0 and 1. Setting to 0 does not swap.'/>
    <member name='delay_rx_data'                         type='ulong' description="Sets the delay of the Rx data relative to Rx frame, measured in 1/2 DATA_CLK cycles for DDR and full DATA_CLK cycles for SDR. Valid values are 0, 1, 2, or 3."/>
    <member name='rx_data_clock_delay'                   type='ulong'/>
    <member name='rx_data_delay'                         type='ulong'/>
    <member name='tx_fb_clock_delay'                     type='ulong' description="Delay in multiples of 0.3 ns to add to the FB_CLK_P pin inside the AD9361 in order to account for the setup/hold requirements of the FB_CLK_P and TX data bus pins. Valid range is [0 15]. This value should be calculated using the setup/hold requiremed values and the reported skews in the FPGA bitstream timing report for the FB_CLK_P, TX data bus, and TX_FRAME_P pins."/>
    <member name='tx_data_delay'                         type='ulong' description="Delay in multiples of 0.3 ns to add to the TX data bus and TX_FRAME_P pins inside the AD9361 in order to account for their setup/hold requirements. Valid range is [0 15]. This value should be calculated using the setup/hold requiremed values and the reported skews in the FPGA bitstream timing report for the FB_CLK_P, TX data bus, and TX_FRAME_P pins."/>
  </property>
  <property name='en_state_machine_mode'                 type='ulong'     volatile='1' writable='1'                           description='Get/set the Enable State Machine (ENSM) mode. Value should be set using one of the ENSM_MODE parameters.'/>
  <property name='rx_rf_gain'            arraylength='rx_nchannels' type='long'      volatile='1' writable='1'                description="Get/set the receive RF gain for the selected channel. The gain is in dB. Note that the written value to the second index of this property will not be applied when this worker's ad9361_rf_phy.pdata.rx2tx2 property member is false."/>
  <property name='rx_rf_bandwidth'                       type='ulong'     volatile='1' writable='1' default='18e6'            description='Get/set the RX RF bandwidth. The bandwidth is in Hz.'/>
  <property name='rx_sampling_freq'                      type='ulong'     volatile='1' writable='1'                           description='Get/set the RX sampling frequency. The frequency is in Hz.'/>
  <property name='rx_lo_freq'                            type='ulonglong' volatile='1' writable='1' default='2.4e9'           description='Get/set the RX LO frequency. The frequency is in Hz.'/>
  <property name='rx_lo_int_ext'                         type='uchar'     writable='1' default='INT_LO'          description='Switch between the internal and external LO. The RX LO is affected.'/>
  <property name='rx_rssi'               arraylength='rx_nchannels' type='struct'    volatile='1'                             description='Get the RSSI for the selected channel.'>
    <member name='ant'                                   type='ulong' description='Antenna number for which RSSI is reported.'/>
    <member name='symbol'                                type='ulong' description='Runtime RSSI.'/>
    <member name='preamble'                              type='ulong' description='Initial RSSI.'/>
    <member name='multiplier'                            type='long'  description='Multiplier to convert reported RSSI.'/>
    <member name='duration'                              type='uchar' description='Duration to be considered for measuring.'/>
  </property>
  <property name='rx_gain_control_mode'  arraylength='rx_nchannels' type='uchar'     volatile='1' writable='1' default='RF_GAIN_MGC,RF_GAIN_MGC' description="Get/set the gain control mode for the selected channel. Note that, when this worker's ad9361_rf_phy.pdata.rx2tx2 property member is false, the value read from the second index of this property should be ignored and the value written to the second index won't be applied."/>
  <property name='rx_fir_config_write'                   type='struct' default='rx 0x83,rx_gain 0,rx_dec 1,rx_coef {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},rx_coef_size 128'              writable='1'            >
    <member name='rx'                                    type='ulong' />
    <member name='rx_gain'                               type='long'  />
    <member name='rx_dec'                                type='ulong' />
    <member name='rx_coef'             arraylength='128' type='short' />
    <member name='rx_coef_size'                          type='uchar' />
    <!-- member name='rx_path_clks'          arraylength='6' type='ulong' /--> <!-- rx_path_clks is a member of the struct but ad9361_set_rx_fir_config ignores this value, commented it out to avoid the scenario where end user thinks they are setting this value when they really aren't -->
    <!-- member name='rx_bandwidth'                          type='ulong' /--> <!-- rx_bandwidth is a member of the struct but ad9361_set_rx_fir_config ignores this value, commented it out to avoid the scenario where end user thinks they are setting this value when they really aren't -->
  </property>
  <property name='rx_fir_config_read'    arraylength='rx_nchannels' type='struct' volatile='1'    description="Note that the readback value of the second index of this property should be ignored when this worker's ad9361_rf_phy.pdata.rx2tx2 property member is false."             >
    <!-- member name='rx'                                    type='ulong' description=''/--> <!-- rx is a member of the struct but the information conveyed is redundant -->
    <member name='rx_gain'                               type='long'  />
    <member name='rx_dec'                                type='ulong' />
    <member name='rx_coef'             arraylength='128' type='short' />
    <member name='rx_coef_size'                          type='uchar' />
    <!-- member name='rx_path_clks'          arraylength='6' type='ulong' /--> <!-- rx_path_clks is a member of the struct but ad9361_set_rx_fir_config ignores this value, commented it out to avoid the scenario where end user thinks they are setting this value when they really aren't -->
    <!-- member name='rx_bandwidth'                          type='ulong' /--> <!-- rx_bandwidth is a member of the struct but ad9361_set_rx_fir_config ignores this value, commented it out to avoid the scenario where end user thinks they are setting this value when they really aren't -->
  </property>
  <property name='rx_fir_en_dis'                         type='uchar'     volatile='1' writable='1' default='DISABLE' description='Get/set the status of the RX FIR filter. The status is one of the parameter values ENABLE or DISABLE.'/>
  <property name='rx_rfdc_track_en_dis'                  type='uchar'     volatile='1' writable='1' default='DISABLE' description='Get/set the status of the RX RFDC Tracking. The status is one of the parameter values ENABLE or DISABLE.'/>
  <property name='rx_bbdc_track_en_dis'                  type='uchar'     volatile='1' writable='1' default='DISABLE' description='Get/set the status of the RX BasebandDC Tracking. The status is one of the parameter values ENABLE or DISABLE.'/>

  <property name='rx_quad_track_en_dis'                  type='uchar'     volatile='1' writable='1' default='DISABLE' description='Get/set the status of the RX Quadrate Tracking. The status is one of the parameter values ENABLE or DISABLE.'/>
  <property name='rx_rf_port_input'                      type='ulong'     volatile='1' writable='1' default='A_BALANCED' description='Get/set the RX RF input port. Accepted values: one of the parameter values A_BALANCED, B_BALANCED, C_BALANCED, A_N, A_P, B_N, B_P, C_N, C_P, TX_MON1, TX_MON_2, TX_MON1_2. '/>
  <property name='rx_fastlock_store'                     type='ulong'                  writable='1'             description='Store RX fastlock profile. Writing a value will initiate the process of creating an RX fast lock profile and store it in the AD9361 in the RX profile index indicated by the value written.'/>
  <property name='rx_fastlock_recall'                    type='ulong'                  writable='1'             description='Recall specified RX fastlock profile. Writing a value will initiate the process of applying an RX fast lock profile that was previously stored inside the AD9361. The written value indicates the index of the RX profile to be applied.'/>
  <property name='rx_fastlock_load'                      type='struct'                 writable='1'            >
    <member name='ad9361_profile_id'                     type='ulong'                       description="Profile ID/index of the AD9361 profile which is to be overwritten by the indicated worker profile."/>
    <member name='worker_profile_id'                     type='ulong'                       description="Profile ID of the worker profile which will be loaded into the AD9361."/>
  </property>
  <property name='rx_fastlock_save'                      type='struct'                 writable='1'            >
    <member name='ad9361_profile_id'                     type='ulong'                       description="Profile ID/index of the AD9361 profile which will be saved into a worker profile (i.e. in memory within this worker)."/>
    <member name='worker_profile_id'                     type='ulong'                       description="Profile ID to assign to the profile saved in this worker's memory. This is for future record keeping of profiles saved within this worker."/>
  </property>
  <property name='tx_attenuation'        arraylength='tx_nchannels' type='ulong'     volatile='1' writable='1' default='1000,1000' description="Get/set the transmit attenuation for the selected channel. The attenuation is in millidB. Values written will be rounded down to the nearest 250 millidB. Note that the written value to the second index of this property will not be applied when this worker's ad9361_rf_phy.pdata.rx2tx2 property member is false."/>
  <property name='tx_rf_bandwidth'                       type='ulong'     volatile='1' writable='1' default='18e6'            description='Get/set the TX RF bandwidth. The bandwidth is in Hz.'/>
  <property name='tx_sampling_freq'                      type='ulong'     volatile='1' writable='1'                           description='Get/set the TX sampling frequency. The frequency is in Hz.'/>
  <property name='tx_lo_freq'                            type='ulonglong' volatile='1' writable='1' default='2.4e9'           description='Get/set the TX LO frequency. The frequency is in Hz.'/>
  <property name='tx_lo_int_ext'                         type='uchar'     writable='1' default='INT_LO'          description='Switch between the internal and external LO. The TX LO is affected.'/>
  <property name='tx_fir_config_write'                   type='struct'  default='tx 0x03,tx_gain 0,tx_int 1,tx_coef {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},tx_coef_size 128'             writable='1'            >
    <member name='tx'                                    type='ulong' />
    <member name='tx_gain'                               type='long'  />
    <member name='tx_int'                                type='ulong' />
    <member name='tx_coef'             arraylength='128' type='short' />
    <member name='tx_coef_size'                          type='uchar' />
    <!-- member name='tx_path_clks'          arraylength='6' type='ulong' /--> <!-- tx_path_clks is a member of the struct but ad9361_set_tx_fir_config ignores this value, commented it out to avoid the scenario where end user thinks they are setting this value when they really aren't -->
    <!-- member name='tx_bandwidth'                          type='ulong' /--> <!-- tx_bandwidth is a member of the struct but ad9361_set_tx_fir_config ignores this value, commented it out to avoid the scenario where end user thinks they are setting this value when they really aren't -->
  </property>
  <property name='tx_fir_config_read'    arraylength='tx_nchannels' type='struct' volatile='1'    description="Note that the readback value of the second index of this property should be ignored when this worker's ad9361_rf_phy.pdata.rx2tx2 property member is false."             >
    <!-- member name='tx'                                    type='ulong' description=''/--> <!-- tx is a member of the struct but the information conveyed is redundant -->
    <member name='tx_gain'                               type='long'  />
    <member name='tx_int'                                type='ulong' />
    <member name='tx_coef'             arraylength='128' type='short' />
    <member name='tx_coef_size'                          type='uchar' />
    <!-- member name='tx_path_clks'          arraylength='6' type='ulong' /--> <!-- tx_path_clks is a member of the struct but ad9361_set_tx_fir_config ignores this value, commented it out to avoid the scenario where end user thinks they are setting this value when they really aren't -->
    <!-- member name='tx_bandwidth'                          type='ulong' /--> <!-- tx_bandwidth is a member of the struct but ad9361_set_tx_fir_config ignores this value, commented it out to avoid the scenario where end user thinks they are setting this value when they really aren't -->
  </property>
  <property name='tx_fir_en_dis'                         type='uchar'     volatile='1' writable='1' default='DISABLE' description='Get/set the status of the TX FIR filter. The status is one of the parameter values ENABLE or DISABLE.'/>
  <property name='tx_rssi'               arraylength='tx_nchannels' type='ulong'     volatile='1'                             description="Get the TX RSSI for the selected channel. The value read represents the RSSI in millidB. Note that the readback value of the second index of this property should be ignored when this worker's ad9361_rf_phy.pdata.rx2tx2 property member is false."/>
  <property name='tx_rf_port_output'                     type='ulong'     volatile='1' writable='1' default='TXA' description='Get/set the TX RF output port.'/>
  <property name='tx_auto_cal_en_dis'                    type='uchar'     volatile='1' writable='1' default='DISABLE' description='Get/set the status of the auto calibration flag. The value should be one of the parameter values ENABLE or DISABLE.'/>
  <property name='tx_fastlock_store'                     type='ulong'                  writable='1'             description='Store TX fastlock profile. Writing a value will initiate the process of creating a TX fast lock profile and store it in the AD9361 in the TX profile index indicated by the value written.'/>
  <property name='tx_fastlock_recall'                    type='ulong'                  writable='1'             description='Recall specified TX fastlock profile. Writing a value will initiate the process of applying an TX fast lock profile that was previously stored inside the AD9361. The written value indicates the index of the TX profile to be applied.'/>
  <property name='tx_fastlock_load'                      type='struct'                 writable='1'            >
    <member name='ad9361_profile_id'                     type='ulong'                       description="Profile ID/index of the AD9361 profile which is to be overwritten by the indicated worker profile."/>
    <member name='worker_profile_id'                     type='ulong'                       description="Profile ID of the worker profile which will be loaded into the AD9361."/>
  </property>
  <property name='tx_fastlock_save'                      type='struct'                 writable='1'            >
    <member name='ad9361_profile_id'                     type='ulong'                       description="Profile ID/index of the AD9361 profile which will be saved into a worker profile (i.e. in memory within this worker)."/>
    <member name='worker_profile_id'                     type='ulong'                       description="Profile ID to assign to the profile saved in this worker's memory. This is for future record keeping of profiles saved within this worker."/>
  </property>
  <property name='trx_path_clks'                         type='struct'    volatile='1' writable='1' description='Set the RX and TX path rates.'>
    <member name='rx_path_clks'          arraylength='NUM_RX_CLOCKS' type='ulong' description='RX path rates buffer. Indices are indicated bye one of the parameter values BPLL_FREQ, ADC_FREQ, R2_FREQ, R1_FREQ, CLKRF_FREQ, and RX_SAMPL_FREQ.'/>
    <member name='tx_path_clks'          arraylength='NUM_TX_CLOCKS' type='ulong' description='TX path rates buffer. Indices are indicated bye one of the parameter values IGNORE,    DAC_FREQ, T2_FREQ, T1_FREQ, CLKTF_FREQ, and TX_SAMPL_FREQ.'/>
  </property>
  <property name='no_ch_mode'                            type='uchar'                  writable='1' description='Set the number of channels mode. Accepted values are one of the parameter values MODE_1x1 or MODE_2x2.'/>
  <!--property name='do_mcs'/--> <!-- TODO / FIXME - fill in this functionality, which would require synchronization with another instance of this worker somehow... -->
  <property name='trx_fir_en_dis'                        type='uchar'                  writable='1' description='Enable/disable the TRX FIR filters. Accepted values are one of the parameter values ENABLE or DISABLE.'/>
  <property name='trx_rate_gov'                          type='ulong'     volatile='1' writable='1' description='Get/set the OSR rate governor. Accepted values are one of the parameter values HIGHEST_OSR or NOMINAL_OSR.'/>
  <property name='do_calib'                              type='struct'                 writable='1' description='Perform the selected calibration.'>
    <member name='cal'                                   type='ulong' description='The selected calibration. Accepted values are one of the parameter values TX_QUAD_CAL or RFDC_CAL.'/>
    <member name='arg'                                   type='long'  description='For TX_QUAD_CAL - the optional RX phase value overwrite (set to zero).'/>
  </property>
  <property name='trx_load_enable_fir'                   type='struct'                 writable='1' description='Load and enable TRX FIR filters configurations.'>
    <member name='rx'                                    type='ulong'/>
    <member name='rx_gain'                               type='long' />
    <member name='rx_dec'                                type='ulong'/>
    <member name='rx_coef'             arraylength='128' type='short'/>
    <member name='rx_coef_size'                          type='uchar'/>
    <member name='rx_path_clks'          arraylength='6' type='ulong'/>
    <member name='rx_bandwidth'                          type='ulong'/>
    <member name='tx'                                    type='ulong'/>
    <member name='tx_gain'                               type='long' />
    <member name='tx_int'                                type='ulong'/>
    <member name='tx_coef'             arraylength='128' type='short'/>
    <member name='tx_coef_size'                          type='uchar'/>
    <member name='tx_path_clks'          arraylength='6' type='ulong'/>
    <member name='tx_bandwidth'                          type='ulong'/>
  </property>
  <property name='do_dcxo_tune_coarse'                   type='ulong'                  writable='1' description='Do DCXO coarse tuning.'/>
  <property name='do_dcxo_tune_fine'                     type='ulong'                  writable='1' description='Do DCXO fine tuning.'/>
  <property name='temperature'                           type='long'      volatile='1'              description='Get the temperature in millidegrees C .'/>

  <!--****** PROPERTIES CORRESPONDING TO libad9361 "ADVANCED" API (ad9361.h) *****-->

  <property name='bist_loopback'                         type='long'      volatile='1' writable='1' description="BIST loopback mode. Valid values are 0 (disables loopback), 1 (loopback AD9361 internal TX-RX), or 2 (loopback (FPGA internal RX-.TX). While a value of 2 is handled by no-os, it is not expected to work with OpenCPI's AD9361 device workers"/>
  <property name='bist_prbs'                             type='uchar'     volatile='1' writable='1' description='BIST mode. Valid values are either BIST_DISABLE or BIST_INJ_RX.'/>
  <property name='bist_tone'                             type='struct'    volatile='1' writable='1' description='BIST tone. Valid values are either BIST_DISABLE, BIST_INJ_TX, or BIST_INJ_RX.'>
    <member name='mode'                                  type='uchar'/>
    <member name='freq_Hz'                               type='ulong'/>
    <member name='level_dB'                              type='ulong'/>
    <member name='mask'                                  type='ulong' description='Valid values are 0, 1, 2, 4, or 8 for no masking, chan 1 I, chan 1 Q, chan 2 I, chan 2 Q masking, respectively.'/>
  </property>

  <!--  PROPERTIES CORRESPONDING TO FUNCTIONALITY IMPLEMENTED OUTSIDE libad9361   -->

  <property name='DATA_CLK_Delay' type='ushort'
                                  volatile='1'
                                  description='This value affects the DATA_CLK
                                    data delay. The typical delay is
                                    approximately 0.3ns/LSB. Minimum delay
                                    setting is 0x0 and maximum delay is 0xF.'/>
  <property name='Rx_Data_Delay' type='ushort'
                                 volatile='1'
                                 description='This value affects the DATA_CLK
                                   data delay. The typical delay is
                                   approximately 0.3ns/LSB. Rx Frame is delayed
                                   the same amount as the data port bits.
                                   Minimum delay setting is 0x0 and maximum
                                   delay is 0xF.'/>
  <property name='FB_CLK_Delay' type='ushort'
                                volatile='1'
                                description='This setting functions the same as
                                  DATA_CLK_Delay but affects the FB_CLK.'/>
  <property name='Tx_Data_Delay' type='ushort'
                                 volatile='1'
                                 description='This setting functions the same as
                                   Rx_Data_Delay but affects the Tx_FRAME and TX
                                   Data bits. Tx frame sync is delayed the same
                                  amount as the data port bits.'/>
  <property name='THB3_Enable_and_Interp' type='enum'
                                          enums='Interpolate_by_1_no_filtering,
                                                 Interpolate_by_2_half_band_filter,
                                                 Interpolate_by_3_and_filter,
                                                 Invalid'
                                          volatile='1'
                                          description='Note that there are
                                            several functions that calculate
                                            digital filter settings. The
                                            ad9361_calculate_rf_clock_chain
                                            function calculates all Rx and Tx
                                            rates. This sets interpolation of
                                            the digital filter that feeds the
                                            DAC. The purpose of this property is
                                            to expose this value as it exists on
                                            the AD9361 IC in order to precisely
                                            calculate the current on-chip
                                            (in-situ) nominal DAC clock rate
                                            (No-OS does not provide a method for
                                            high-precision calculation of the
                                            nominal DAC rate).'/>
  <property name='THB2_Enable' type='bool'
                               volatile='1'
                               description='Note that there are several
                                 functions that calculate digital filter
                                 settings. The ad9361_calculate_rf_clock_chain
                                 function calculates all Rx and Tx rates.
                                 Setting to true enables the interpolate-by-2
                                 THB2 half-band filter. Setting to false
                                 bypasses the filter. The purpose of this
                                 property is to expose this value as it exists
                                 on the AD9361 IC in order to precisely
                                 calculate the current on-chip (in-situ) nominal
                                 DAC clock rate (No-OS does not provide a method
                                 for high-precision calculation of the nominal
                                 DAC rate).'/>
  <property name='THB1_Enable' type='bool'
                               volatile='1'
                               description='Note that there are several
                                 functions that calculate digital filter
                                 settings. The ad9361_calculate_rf_clock_chain
                                 function calculates all Rx and Tx rates.
                                 Setting to true enables the interpolate-by-2
                                 THB1 half-band filter. Setting to false
                                 bypasses the filter. The purpose of this
                                 property is to expose this value as it exists
                                 on the AD9361 IC in order to precisely
                                 calculate the current on-chip (in-situ) nominal
                                 DAC clock rate (No-OS does not provide a method
                                 for high-precision calculation of the nominal
                                 DAC rate).'/>
  <property name='RHB3_Enable_and_Decimation' type='enum'
                                              enums='Decimate_by_1_no_filtering,
                                                     Decimate_by_2_half_band_filter,
                                                     Decimate_by_3_and_filter,
                                                     Invalid'
                                              volatile='1'
                                              description='Note that there are
                                                several functions that calculate
                                                digital filter settings. The
                                                ad9361_calculate_rf_clock_chain
                                                function calculates all Rx and
                                                Tx rates. This sets decimation
                                                of the first filter stage after
                                                the ADC. The purpose of this
                                                property is to expose this value
                                                as it exists on the AD9361 IC
                                                in order to precisely calculate
                                                the current on-chip (in-situ)
                                                nominal ADC clock rate (No-OS
                                                does not provide a method for
                                                high-precision calculation of
                                                the nominal ADC rate).'/>
  <property name='RHB2_Enable' type='bool'
                               volatile='1'
                               description='Note that there are several
                                 functions that calculate digital filter
                                 settings. The ad9361_calculate_rf_clock_chain
                                 function calculates all Rx and Tx rates.
                                 Setting to true enables the decimate-by-2
                                 RHB2 half-band filter. Setting to false
                                 bypasses the filter. The purpose of this
                                 property is to expose this value as it exists
                                 on the AD9361 IC in order to precisely
                                 calculate the current on-chip (in-situ) nominal
                                 ADC clock rate (No-OS does not provide a method
                                 for high-precision calculation of the nominal
                                 ADC rate).'/>
  <property name='RHB1_Enable' type='bool'
                               volatile='1'
                               description='Note that there are several
                                 functions that calculate digital filter
                                 settings. The ad9361_calculate_rf_clock_chain
                                 function calculates all Rx and Tx rates.
                                 Setting to true enables the decimate-by-2
                                 RHB1 half-band filter. Setting to false
                                 bypasses the filter. The purpose of this
                                 property is to expose this value as it exists
                                 on the AD9361 IC in order to precisely
                                 calculate the current on-chip (in-situ) nominal
                                 ADC clock rate (No-OS does not provide a method
                                 for high-precision calculation of the nominal
                                 ADC rate).'/>
  <property name='DAC_Clk_div2' type='bool'
                                volatile='1'
                                description='The ad9361_calculate_rf_clock_chain
                                  function configures this value. When false,
                                  the DAC clock rate equals the ADC clock rate.
                                  When true, the DAC clock equals 1/2 of the ADC
                                  rate. The purpose of this property is to
                                  expose this value as it exists on the AD9361
                                  IC in order to precisely calculate the current
                                  on-chip (in-situ) nominal DAC clock rate
                                  (No-OS does not provide a method for
                                  high-precision calculation of the nominal DAC
                                  rate).'/>
  <property name='BBPLL_Divider' type='enum'
                                 enums='invalid,1,2,3,4,5,6'
                                 volatile='1'
                                 description='The ad9361_bbpll_set_rate function
                                   controls this value. The ADC clock rate
                                   equals the BBPLL divided by the factor which
                                   is a function of this value, shown in the
                                   following equation.
                                   ADC Clock Rate=BBPLL Clock Rate /
                                                  [2^(BBPLL Divider)].
                                   BBPLL Divider is valid from 1 through 6.'/>
  <property name='Fractional_BB_Frequency_Word' type='ulong'
                                                volatile='1'
                                                description='Fractional BB
                                                             Frequency Word.'/>
  <property name='Integer_BB_Frequency_Word' type='ushort'
                                             volatile='1'
                                             description='Integer BB Frequency
                                                          Word.'/>
  <property name='BBPLL_Ref_Clock_Scaler' type='float'
                                          volatile='1'
                                          description='Ref Clock Scaler. The
                                            reference clock frequency is scaled
                                            before it enters the BBPLL. Only
                                            possible scaler values are: x1;
                                            x1/2; x1/4; x2.'/>
  <property name='Tx_BBF_Tune_Divider' type='enum'
                                       enums='invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511'
                                       volatile='1'
                                       description='Tx BBF Tune Divider. The
                                         baseband Tx analog filter calibration
                                         sets the 3dB cutoff frequency of the
                                         third-order Butterworth Tx anti-imaging
                                         filter based on the Tx BBF Tune
                                         Divider. The third-order Tx filter is
                                         located just after the DAC in the Tx
                                         signal path and is normally calibrated
                                         to 1.6x the BBBW. Note that the BBBW is
                                         half the complex bandwidth. To set the
                                         cutoff frequency value, the BBPLL is
                                         divided down using a divide by 1 to 511
                                         divider dedicated to the Tx tuner
                                         block.'/>
  <property name='Tx_Secondary_Filter_Resistor' type='enum'
                                                enums='invalid,800,400,200,100'
                                                volatile='1'
                                                description='Secondary Tx filter
                                                  resistor, which, along with
                                                  the secondary Tx Capacitor,
                                                  sets the 3 dB corner frequency
                                                  of the secondary single-pole
                                                  Tx RC filter via the equation
                                                  1/(2*pi*R*C). Value is
                                                  represented in ohms.'/>
  <property name='Tx_Secondary_Filter_Capacitor' type='ushort'
                                                 volatile='1'
                                                 description='Secondary Tx
                                                   filter capacitor, which,
                                                   along with the secondary Tx
                                                   Resistor, sets the 3 dB
                                                   corner frequency of the
                                                   secondary single-pole Tx RC
                                                   filter via the equation
                                                   1/(2*pi*R*C). Resolution:
                                                   1pF/LSB. Total capacitance
                                                   (C in previous equation) is
                                                   12pF + (
                                                   Tx_Secondary_Filter_Capacitor
                                                    \*1pF)'/>
  <property name='Rx_BBF_Tune_Divide' type='enum'
                                      enums='invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511'
                                      volatile='1'
                                      description='Rx BBF Tune Divide. The
                                        tuning algorithm generates a tune clock
                                        derived from the BBPLL frequency. This
                                        divider outputs the tune clock, set per
                                        for following equation. Rx BBF Tune
                                        Divider[8:0] = ceil(BBPLL Frequency x
                                        ln(2) / (BBBW x 1.4 x 2 x pi)). The
                                        range of the divider is 1 to 511.'/>
  <property name='bb_pll_is_locked' type='bool' volatile='1'/>
  <property name='rx_pll_is_locked' type='enum' enums='false,true,unknown' volatile='1'/>
  <property name='rx_fastlock_delete'                    type='ulong'                  writable='1' description="Performs a deletion of an RX fastlock profile saved in this worker's memory. The profile which is deleted is the one whose profile ID matches the value written to this property."/>
  <property name='tx_pll_is_locked' type='enum' enums='false,true,unknown' volatile='1'/>
  <property name='tx_fastlock_delete'                    type='ulong'                  writable='1' description="Performs a deletion of an RX fastlock profile saved in this worker's memory. The profile which is deleted is the one whose profile ID matches the value written to this property."/>
  <property name='rx_vco_divider'   type='enum' enums='2,4,8,16,32,64,128,external_2,invalid' volatile='1'/>
  <property name='rx_vco_n_integer'    type='ushort' volatile='1'/>
  <property name='rx_vco_n_fractional' type='ulong'  volatile='1'/>
  <property name='Rx_Ref_Divider' type='float'
                                  volatile='1'
                                  description='Rx Ref Divider. This controls the
                                    Rx path divider which scales the rate of the
                                    analog clock which is input to the Rx PLL
                                    Synthesizer (which generates the Rx LO
                                    clock). Only possible ratios are: 1, 1/2,
                                    1/4, 2. The purpose of this property is to
                                    expose this value as it exists on the AD9361
                                    IC in order to precisely calculate the
                                    current on-chip (in-situ) nominal Rx LO
                                    frequency value (No-OS does not provide a
                                    method for high-precision calculation of the
                                    nominal LO frequencies).'/>
  <property name='tx_vco_divider'   type='enum' enums='2,4,8,16,32,64,128,external_2,invalid' volatile='1'/>
  <property name='tx_vco_n_integer'    type='ushort' volatile='1'/>
  <property name='tx_vco_n_fractional' type='ulong'  volatile='1'/>
  <property name='Tx_Ref_Divider' type='float'
                                  volatile='1'
                                  description='Tx Ref Divider. This controls the
                                    Tx path divider which scales the rate of the
                                    analog clock which is input to the Tx PLL
                                    Synthesizer (which generates the Tx LO
                                    clock). Only possible ratios are: 1, 1/2,
                                    1/4, 2. The purpose of this property is to
                                    expose this value as it exists on the AD9361
                                    IC in order to precisely calculate the
                                    current on-chip (in-situ) nominal Tx LO
                                    frequency value (No-OS does not provide a
                                    method for high-precision calculation of the
                                    nominal LO frequencies).'/>
  <property name='Tx_Channel_Swap'  type='bool' volatile='1' description="Setting this to true swaps the positions of Tx1 and Tx2 samples."/>
  <property name='Rx_Channel_Swap'  type='bool' volatile='1' description="Setting this to true swaps the positions of Rx1 and Rx2 samples."/>
  <property name='LVDS'             type='bool' volatile='1' description="Value is true if bitstream monitored by instance of this worker was built to use LVDS mode for Data/clock/frame signals, and false if CMOS mode was used."/>
  <property name='single_port'      type='bool' volatile='1' description="Value is true if bitstream monitored by instance of this worker was built to use single port, and false if dual ports."/>
  <property name='swap_ports'       type='bool' volatile='1' description="Value is true if bitstream monitored by instance of this worker was built to swap Port 0 and Port 1, and false if there was no swap."/>
  <property name='half_duplex'      type='bool' volatile='1' description="Value is true if bitstream monitored by instance of this worker was built to use half duplex mode, and false if full duplex mode."/>
  <property name='data_rate_config' type='enum' enums='SDR,DDR'     volatile='1' description="Value indicates which data rate mode (SDR/DDR) the bitstream was built to use."/>
  <property name='DATA_CLK_P_rate_Hz' type='double' volatile='1'/>
  <property name='BIST_Mask_Channel_2_Q_data' type='bool' volatile='1' writable='1' description='Setting zeros out Channel 2 Q data.'/> <!-- BIST mode only? -->
  <property name='BIST_Mask_Channel_2_I_data' type='bool' volatile='1' writable='1' description='Setting zeros out Channel 2 I data.'/> <!-- BIST mode only? -->
  <property name='BIST_Mask_Channel_1_Q_data' type='bool' volatile='1' writable='1' description='Setting zeros out Channel 1 Q data.'/> <!-- BIST mode only? -->
  <property name='BIST_Mask_Channel_1_I_data' type='bool' volatile='1' writable='1' description='Setting zeros out Channel 1 I data.'/> <!-- BIST mode only? -->

</componentspec>

Properties

rx_nchannels
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
tx_nchannels
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
ENABLE
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
DISABLE
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
A_BALANCED
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
B_BALANCED
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
C_BALANCED
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
A_N
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 3
A_P
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 4
B_N
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 5
B_P
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 6
C_N
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 7
C_P
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 8
TX_MON1
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 9
TX_MON2
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 10
TX_MON1_2
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 11
TXA
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
TXB
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
ENSM_MODE_TX
- Type: long
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
ENSM_MODE_RX
- Type: long
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
ENSM_MODE_ALERT
- Type: long
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
ENSM_MODE_FDD
- Type: long
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 3
ENSM_MODE_WAIT
- Type: long
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 4
ENSM_MODE_SLEEP
- Type: long
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 5
ENSM_MODE_PINCTRL
- Type: long
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 6
ENSM_MODE_PINCTRL_FDD_INDEP
- Type: long
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 7
INT_LO
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
EXT_LO
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
RF_GAIN_MGC
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
RF_GAIN_FASTATTACK_AGC
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
RF_GAIN_SLOWATTACK_AGC
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
RF_GAIN_HYBRID_AGC
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 3
FIR_TX1
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0x01
FIR_TX2
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0x02
FIR_TX1_TX2
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0x03
FIR_RX1
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0x81
FIR_RX2
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0x82
FIR_RX1_RX2
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0x83
FIR_IS_RX
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0x80
RX_1
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
RX_2
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
TX_1
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
TX_2
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
BPLL_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
ADC_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
R2_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
R1_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 3
CLKRF_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 4
RX_SAMPL_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 5
NUM_RX_CLOCKS
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 6
IGNORE
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
DAC_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
T2_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
T1_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 3
CLKTF_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 4
TX_SAMPL_FREQ
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 5
NUM_TX_CLOCKS
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 6
BIST_DISABLE
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
BIST_INJ_TX
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
BIST_INJ_RX
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
MODE_1x1
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
MODE_2x2
- Type: uchar
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 2
HIGHEST_OSR
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 0
NOMINAL_OSR
- Type: ulong
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 1
ad9361_rf_phy:.
- Type: struct
  - Members:
    - clk_refin:
      - rate:
        
        data_type: ulong
    - pdata:
      - rx2tx2:
        
        data_type: bool
      - fdd:
        
        data_type: bool
      - use_extclk:
        
        data_type: bool
      - dcxo_coarse:
        
        data_type: ulong
      - dcxo_fine:
        
        data_type: ulong
      - rx1tx1_mode_use_rx_num:
        
        data_type: ulong
      - rx1tx1_mode_use_tx_num:
        
        data_type: ulong
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
ad9361_init: Initialize the AD9361 part.
- Type: struct
  - Members:
    - reference_clk_rate:
      - data_type: ulong
    - one_rx_one_tx_mode_use_rx_num:
      - data_type: uchar
    - one_rx_one_tx_mode_use_tx_num:
      - data_type: uchar
    - frequency_division_duplex_mode_enable:
      - data_type: uchar
    - xo_disable_use_ext_refclk_enable:
      - data_type: uchar
    - two_t_two_r_timing_enable:
      - data_type: bool
    - pp_tx_swap_enable:
      - data_type: uchar
    - pp_rx_swap_enable:
      - data_type: uchar
    - tx_channel_swap_enable:
      - data_type: uchar
    - rx_channel_swap_enable:
      - data_type: uchar
    - delay_rx_data:
      - data_type: ulong
    - rx_data_clock_delay:
      - data_type: ulong
    - rx_data_delay:
      - data_type: ulong
    - tx_fb_clock_delay:
      - data_type: ulong
    - tx_data_delay:
      - data_type: ulong
- Access:
  - Parameter: False
  - Writable: False
  - Initial: True
  - Volatile: False
- Default value: reference_clk_rate 40e6,one_rx_one_tx_mode_use_rx_num 1,
  one_rx_one_tx_mode_use_tx_num 1,frequency_division_duplex_mode_enable 1,
  xo_disable_use_ext_refclk_enable 0,two_t_two_r_timing_enable 0,
  pp_tx_swap_enable 1,pp_rx_swap_enable 1,tx_channel_swap_enable 1,
  rx_channel_swap_enable 1,delay_rx_data 0,rx_data_clock_delay 0,rx_data_delay 4,
  tx_fb_clock_delay 7,tx_data_delay 0
en_state_machine_mode: Get/set the Enable State Machine (ENSM) mode. Value should be set using one of the ENSM_MODE parameters.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
rx_rf_gain: Get/set the receive RF gain for the selected channel. The gain is in dB. Note that the written value to the second index of this property will not be applied when this worker’s ad9361_rf_phy.pdata.rx2tx2 property member is false.
- Type: long
  - Array dimensions: ['rx_nchannels']
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
rx_rf_bandwidth: Get/set the RX RF bandwidth. The bandwidth is in Hz.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: 18e6
rx_sampling_freq: Get/set the RX sampling frequency. The frequency is in Hz.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
rx_lo_freq: Get/set the RX LO frequency. The frequency is in Hz.
- Type: ulonglong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: 2.4e9
rx_lo_int_ext: Switch between the internal and external LO. The RX LO is affected.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: INT_LO
rx_rssi: Get the RSSI for the selected channel.
- Type: struct
  - Array dimensions: ['rx_nchannels']
  - Members:
    - ant:
      - data_type: ulong
    - symbol:
      - data_type: ulong
    - preamble:
      - data_type: ulong
    - multiplier:
      - data_type: long
    - duration:
      - data_type: uchar
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
rx_gain_control_mode: Get/set the gain control mode for the selected channel. Note that, when this worker’s ad9361_rf_phy.pdata.rx2tx2 property member is false, the value read from the second index of this property should be ignored and the value written to the second index won’t be applied.
- Type: uchar
  - Array dimensions: ['rx_nchannels']
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: RF_GAIN_MGC,RF_GAIN_MGC
rx_fir_config_write
- Type: struct
  - Members:
    - rx:
      - data_type: ulong
    - rx_gain:
      - data_type: long
    - rx_dec:
      - data_type: ulong
    - rx_coef:
      - data_type: short
      - arraydimensions: ['128']
    - rx_coef_size:
      - data_type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: rx 0x83,rx_gain 0,rx_dec 1,rx_coef {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},rx_coef_size 128
rx_fir_config_read: Note that the readback value of the second index of this property should be ignored when this worker’s ad9361_rf_phy.pdata.rx2tx2 property member is false.
- Type: struct
  - Array dimensions: ['rx_nchannels']
  - Members:
    - rx_gain:
      - data_type: long
    - rx_dec:
      - data_type: ulong
    - rx_coef:
      - data_type: short
      - arraydimensions: ['128']
    - rx_coef_size:
      - data_type: uchar
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
rx_fir_en_dis: Get/set the status of the RX FIR filter. The status is one of the parameter values ENABLE or DISABLE.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: DISABLE
rx_rfdc_track_en_dis: Get/set the status of the RX RFDC Tracking. The status is one of the parameter values ENABLE or DISABLE.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: DISABLE
rx_bbdc_track_en_dis: Get/set the status of the RX BasebandDC Tracking. The status is one of the parameter values ENABLE or DISABLE.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: DISABLE
rx_quad_track_en_dis: Get/set the status of the RX Quadrate Tracking. The status is one of the parameter values ENABLE or DISABLE.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: DISABLE
rx_rf_port_input: Get/set the RX RF input port. Accepted values: one of the parameter values A_BALANCED, B_BALANCED, C_BALANCED, A_N, A_P, B_N, B_P, C_N, C_P, TX_MON1, TX_MON_2, TX_MON1_2.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: A_BALANCED
rx_fastlock_store: Store RX fastlock profile. Writing a value will initiate the process of creating an RX fast lock profile and store it in the AD9361 in the RX profile index indicated by the value written.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
rx_fastlock_recall: Recall specified RX fastlock profile. Writing a value will initiate the process of applying an RX fast lock profile that was previously stored inside the AD9361. The written value indicates the index of the RX profile to be applied.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
rx_fastlock_load
- Type: struct
  - Members:
    - ad9361_profile_id:
      - data_type: ulong
    - worker_profile_id:
      - data_type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
rx_fastlock_save
- Type: struct
  - Members:
    - ad9361_profile_id:
      - data_type: ulong
    - worker_profile_id:
      - data_type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
tx_attenuation: Get/set the transmit attenuation for the selected channel. The attenuation is in millidB. Values written will be rounded down to the nearest 250 millidB. Note that the written value to the second index of this property will not be applied when this worker’s ad9361_rf_phy.pdata.rx2tx2 property member is false.
- Type: ulong
  - Array dimensions: ['tx_nchannels']
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: 1000,1000
tx_rf_bandwidth: Get/set the TX RF bandwidth. The bandwidth is in Hz.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: 18e6
tx_sampling_freq: Get/set the TX sampling frequency. The frequency is in Hz.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
tx_lo_freq: Get/set the TX LO frequency. The frequency is in Hz.
- Type: ulonglong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: 2.4e9
tx_lo_int_ext: Switch between the internal and external LO. The TX LO is affected.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: INT_LO
tx_fir_config_write
- Type: struct
  - Members:
    - tx:
      - data_type: ulong
    - tx_gain:
      - data_type: long
    - tx_int:
      - data_type: ulong
    - tx_coef:
      - data_type: short
      - arraydimensions: ['128']
    - tx_coef_size:
      - data_type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: tx 0x03,tx_gain 0,tx_int 1,tx_coef {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},tx_coef_size 128
tx_fir_config_read: Note that the readback value of the second index of this property should be ignored when this worker’s ad9361_rf_phy.pdata.rx2tx2 property member is false.
- Type: struct
  - Array dimensions: ['tx_nchannels']
  - Members:
    - tx_gain:
      - data_type: long
    - tx_int:
      - data_type: ulong
    - tx_coef:
      - data_type: short
      - arraydimensions: ['128']
    - tx_coef_size:
      - data_type: uchar
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
tx_fir_en_dis: Get/set the status of the TX FIR filter. The status is one of the parameter values ENABLE or DISABLE.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: DISABLE
tx_rssi: Get the TX RSSI for the selected channel. The value read represents the RSSI in millidB. Note that the readback value of the second index of this property should be ignored when this worker’s ad9361_rf_phy.pdata.rx2tx2 property member is false.
- Type: ulong
  - Array dimensions: ['tx_nchannels']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
tx_rf_port_output: Get/set the TX RF output port.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: TXA
tx_auto_cal_en_dis: Get/set the status of the auto calibration flag. The value should be one of the parameter values ENABLE or DISABLE.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: DISABLE
tx_fastlock_store: Store TX fastlock profile. Writing a value will initiate the process of creating a TX fast lock profile and store it in the AD9361 in the TX profile index indicated by the value written.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
tx_fastlock_recall: Recall specified TX fastlock profile. Writing a value will initiate the process of applying an TX fast lock profile that was previously stored inside the AD9361. The written value indicates the index of the TX profile to be applied.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
tx_fastlock_load
- Type: struct
  - Members:
    - ad9361_profile_id:
      - data_type: ulong
    - worker_profile_id:
      - data_type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
tx_fastlock_save
- Type: struct
  - Members:
    - ad9361_profile_id:
      - data_type: ulong
    - worker_profile_id:
      - data_type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
trx_path_clks: Set the RX and TX path rates.
- Type: struct
  - Members:
    - rx_path_clks:
      - data_type: ulong
      - arraydimensions: ['NUM_RX_CLOCKS']
    - tx_path_clks:
      - data_type: ulong
      - arraydimensions: ['NUM_TX_CLOCKS']
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
no_ch_mode: Set the number of channels mode. Accepted values are one of the parameter values MODE_1x1 or MODE_2x2.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
trx_fir_en_dis: Enable/disable the TRX FIR filters. Accepted values are one of the parameter values ENABLE or DISABLE.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
trx_rate_gov: Get/set the OSR rate governor. Accepted values are one of the parameter values HIGHEST_OSR or NOMINAL_OSR.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
do_calib: Perform the selected calibration.
- Type: struct
  - Members:
    - cal:
      - data_type: ulong
    - arg:
      - data_type: long
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
trx_load_enable_fir: Load and enable TRX FIR filters configurations.
- Type: struct
  - Members:
    - rx:
      - data_type: ulong
    - rx_gain:
      - data_type: long
    - rx_dec:
      - data_type: ulong
    - rx_coef:
      - data_type: short
      - arraydimensions: ['128']
    - rx_coef_size:
      - data_type: uchar
    - rx_path_clks:
      - data_type: ulong
      - arraydimensions: ['6']
    - rx_bandwidth:
      - data_type: ulong
    - tx:
      - data_type: ulong
    - tx_gain:
      - data_type: long
    - tx_int:
      - data_type: ulong
    - tx_coef:
      - data_type: short
      - arraydimensions: ['128']
    - tx_coef_size:
      - data_type: uchar
    - tx_path_clks:
      - data_type: ulong
      - arraydimensions: ['6']
    - tx_bandwidth:
      - data_type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
do_dcxo_tune_coarse: Do DCXO coarse tuning.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
do_dcxo_tune_fine: Do DCXO fine tuning.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
temperature: Get the temperature in millidegrees C .
- Type: long
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
bist_loopback: BIST loopback mode. Valid values are 0 (disables loopback), 1 (loopback AD9361 internal TX-RX), or 2 (loopback (FPGA internal RX-.TX). While a value of 2 is handled by no-os, it is not expected to work with OpenCPI’s AD9361 device workers.
- Type: long
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
bist_prbs: BIST mode. Valid values are either BIST_DISABLE or BIST_INJ_RX.
- Type: uchar
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
bist_tone: BIST tone. Valid values are either BIST_DISABLE, BIST_INJ_TX, or BIST_INJ_RX.
- Type: struct
  - Members:
    - mode:
      - data_type: uchar
    - freq_Hz:
      - data_type: ulong
    - level_dB:
      - data_type: ulong
    - mask:
      - data_type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
DATA_CLK_Delay: This value affects the DATA_CLK data delay. The typical delay is approximately 0.3ns/LSB. Minimum delay setting is 0x0 and maximum delay is 0xF.
- Type: ushort
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Rx_Data_Delay: This value affects the DATA_CLK data delay. The typical delay is approximately 0.3ns/LSB. Rx Frame is delayed the same amount as the data port bits. Minimum delay setting is 0x0 and maximum delay is 0xF.
- Type: ushort
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
FB_CLK_Delay: This setting functions the same as DATA_CLK_Delay but affects the FB_CLK.
- Type: ushort
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Tx_Data_Delay: This setting functions the same as Rx_Data_Delay but affects the Tx_FRAME and TX Data bits. Tx frame sync is delayed the same amount as the data port bits.
- Type: ushort
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
THB3_Enable_and_Interp: Note that there are several functions that calculate digital filter settings. The ad9361_calculate_rf_clock_chain function calculates all Rx and Tx rates. This sets interpolation of the digital filter that feeds the DAC. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal DAC clock rate (No-OS does not provide a method for high-precision calculation of the nominal DAC rate).
- Type: enum
  - Allowed values: ['Interpolate_by_1_no_filtering', 'Interpolate_by_2_half_band_filter',
    'Interpolate_by_3_and_filter', 'Invalid']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
THB2_Enable: Note that there are several functions that calculate digital filter settings. The ad9361_calculate_rf_clock_chain function calculates all Rx and Tx rates. Setting to true enables the interpolate-by-2 THB2 half-band filter. Setting to false bypasses the filter. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal DAC clock rate (No-OS does not provide a method for high-precision calculation of the nominal DAC rate).
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
THB1_Enable: Note that there are several functions that calculate digital filter settings. The ad9361_calculate_rf_clock_chain function calculates all Rx and Tx rates. Setting to true enables the interpolate-by-2 THB1 half-band filter. Setting to false bypasses the filter. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal DAC clock rate (No-OS does not provide a method for high-precision calculation of the nominal DAC rate).
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
RHB3_Enable_and_Decimation: Note that there are several functions that calculate digital filter settings. The ad9361_calculate_rf_clock_chain function calculates all Rx and Tx rates. This sets decimation of the first filter stage after the ADC. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal ADC clock rate (No-OS does not provide a method for high-precision calculation of the nominal ADC rate).
- Type: enum
  - Allowed values: ['Decimate_by_1_no_filtering', 'Decimate_by_2_half_band_filter',
    'Decimate_by_3_and_filter', 'Invalid']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
RHB2_Enable: Note that there are several functions that calculate digital filter settings. The ad9361_calculate_rf_clock_chain function calculates all Rx and Tx rates. Setting to true enables the decimate-by-2 RHB2 half-band filter. Setting to false bypasses the filter. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal ADC clock rate (No-OS does not provide a method for high-precision calculation of the nominal ADC rate).
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
RHB1_Enable: Note that there are several functions that calculate digital filter settings. The ad9361_calculate_rf_clock_chain function calculates all Rx and Tx rates. Setting to true enables the decimate-by-2 RHB1 half-band filter. Setting to false bypasses the filter. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal ADC clock rate (No-OS does not provide a method for high-precision calculation of the nominal ADC rate).
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
DAC_Clk_div2: The ad9361_calculate_rf_clock_chain function configures this value. When false, the DAC clock rate equals the ADC clock rate. When true, the DAC clock equals 1/2 of the ADC rate. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal DAC clock rate (No-OS does not provide a method for high-precision calculation of the nominal DAC rate).
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
BBPLL_Divider: The ad9361_bbpll_set_rate function controls this value. The ADC clock rate equals the BBPLL divided by the factor which is a function of this value, shown in the following equation. ADC Clock Rate=BBPLL Clock Rate / [2^(BBPLL Divider)]. BBPLL Divider is valid from 1 through 6.
- Type: enum
  - Allowed values: ['invalid', '1', '2', '3', '4', '5', '6']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Fractional_BB_Frequency_Word: Fractional BB Frequency Word.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Integer_BB_Frequency_Word: Integer BB Frequency Word.
- Type: ushort
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
BBPLL_Ref_Clock_Scaler: Ref Clock Scaler. The reference clock frequency is scaled before it enters the BBPLL. Only possible scaler values are: x1; x1/2; x1/4; x2.
- Type: float
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Tx_BBF_Tune_Divider: Tx BBF Tune Divider. The baseband Tx analog filter calibration sets the 3dB cutoff frequency of the third-order Butterworth Tx anti-imaging filter based on the Tx BBF Tune Divider. The third-order Tx filter is located just after the DAC in the Tx signal path and is normally calibrated to 1.6x the BBBW. Note that the BBBW is half the complex bandwidth. To set the cutoff frequency value, the BBPLL is divided down using a divide by 1 to 511 divider dedicated to the Tx tuner block.
- Type: enum
  - Allowed values: ['invalid', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13',
    '14', '15', '16', '17', '18', '19', '20', '21', '22', '23', '24', '25', '26',
    '27', '28', '29', '30', '31', '32', '33', '34', '35', '36', '37', '38', '39',
    '40', '41', '42', '43', '44', '45', '46', '47', '48', '49', '50', '51', '52',
    '53', '54', '55', '56', '57', '58', '59', '60', '61', '62', '63', '64', '65',
    '66', '67', '68', '69', '70', '71', '72', '73', '74', '75', '76', '77', '78',
    '79', '80', '81', '82', '83', '84', '85', '86', '87', '88', '89', '90', '91',
    '92', '93', '94', '95', '96', '97', '98', '99', '100', '101', '102', '103',
    '104', '105', '106', '107', '108', '109', '110', '111', '112', '113', '114',
    '115', '116', '117', '118', '119', '120', '121', '122', '123', '124', '125',
    '126', '127', '128', '129', '130', '131', '132', '133', '134', '135', '136',
    '137', '138', '139', '140', '141', '142', '143', '144', '145', '146', '147',
    '148', '149', '150', '151', '152', '153', '154', '155', '156', '157', '158',
    '159', '160', '161', '162', '163', '164', '165', '166', '167', '168', '169',
    '170', '171', '172', '173', '174', '175', '176', '177', '178', '179', '180',
    '181', '182', '183', '184', '185', '186', '187', '188', '189', '190', '191',
    '192', '193', '194', '195', '196', '197', '198', '199', '200', '201', '202',
    '203', '204', '205', '206', '207', '208', '209', '210', '211', '212', '213',
    '214', '215', '216', '217', '218', '219', '220', '221', '222', '223', '224',
    '225', '226', '227', '228', '229', '230', '231', '232', '233', '234', '235',
    '236', '237', '238', '239', '240', '241', '242', '243', '244', '245', '246',
    '247', '248', '249', '250', '251', '252', '253', '254', '255', '256', '257',
    '258', '259', '260', '261', '262', '263', '264', '265', '266', '267', '268',
    '269', '270', '271', '272', '273', '274', '275', '276', '277', '278', '279',
    '280', '281', '282', '283', '284', '285', '286', '287', '288', '289', '290',
    '291', '292', '293', '294', '295', '296', '297', '298', '299', '300', '301',
    '302', '303', '304', '305', '306', '307', '308', '309', '310', '311', '312',
    '313', '314', '315', '316', '317', '318', '319', '320', '321', '322', '323',
    '324', '325', '326', '327', '328', '329', '330', '331', '332', '333', '334',
    '335', '336', '337', '338', '339', '340', '341', '342', '343', '344', '345',
    '346', '347', '348', '349', '350', '351', '352', '353', '354', '355', '356',
    '357', '358', '359', '360', '361', '362', '363', '364', '365', '366', '367',
    '368', '369', '370', '371', '372', '373', '374', '375', '376', '377', '378',
    '379', '380', '381', '382', '383', '384', '385', '386', '387', '388', '389',
    '390', '391', '392', '393', '394', '395', '396', '397', '398', '399', '400',
    '401', '402', '403', '404', '405', '406', '407', '408', '409', '410', '411',
    '412', '413', '414', '415', '416', '417', '418', '419', '420', '421', '422',
    '423', '424', '425', '426', '427', '428', '429', '430', '431', '432', '433',
    '434', '435', '436', '437', '438', '439', '440', '441', '442', '443', '444',
    '445', '446', '447', '448', '449', '450', '451', '452', '453', '454', '455',
    '456', '457', '458', '459', '460', '461', '462', '463', '464', '465', '466',
    '467', '468', '469', '470', '471', '472', '473', '474', '475', '476', '477',
    '478', '479', '480', '481', '482', '483', '484', '485', '486', '487', '488',
    '489', '490', '491', '492', '493', '494', '495', '496', '497', '498', '499',
    '500', '501', '502', '503', '504', '505', '506', '507', '508', '509', '510',
    '511']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Tx_Secondary_Filter_Resistor: Secondary Tx filter resistor, which, along with the secondary Tx Capacitor, sets the 3 dB corner frequency of the secondary single-pole Tx RC filter via the equation 1/(2*pi*R*C). Value is represented in ohms.
- Type: enum
  - Allowed values: ['invalid', '800', '400', '200', '100']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Tx_Secondary_Filter_Capacitor: Secondary Tx filter capacitor, which, along with the secondary Tx Resistor, sets the 3 dB corner frequency of the secondary single-pole Tx RC filter via the equation 1/(2*pi*R*C). Resolution: 1pF/LSB. Total capacitance (C in previous equation) is 12pF + ( Tx_Secondary_Filter_Capacitor *1pF).
- Type: ushort
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Rx_BBF_Tune_Divide: Rx BBF Tune Divide. The tuning algorithm generates a tune clock derived from the BBPLL frequency. This divider outputs the tune clock, set per for following equation. Rx BBF Tune Divider[8:0] = ceil(BBPLL Frequency x ln(2) / (BBBW x 1.4 x 2 x pi)). The range of the divider is 1 to 511.
- Type: enum
  - Allowed values: ['invalid', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13',
    '14', '15', '16', '17', '18', '19', '20', '21', '22', '23', '24', '25', '26',
    '27', '28', '29', '30', '31', '32', '33', '34', '35', '36', '37', '38', '39',
    '40', '41', '42', '43', '44', '45', '46', '47', '48', '49', '50', '51', '52',
    '53', '54', '55', '56', '57', '58', '59', '60', '61', '62', '63', '64', '65',
    '66', '67', '68', '69', '70', '71', '72', '73', '74', '75', '76', '77', '78',
    '79', '80', '81', '82', '83', '84', '85', '86', '87', '88', '89', '90', '91',
    '92', '93', '94', '95', '96', '97', '98', '99', '100', '101', '102', '103',
    '104', '105', '106', '107', '108', '109', '110', '111', '112', '113', '114',
    '115', '116', '117', '118', '119', '120', '121', '122', '123', '124', '125',
    '126', '127', '128', '129', '130', '131', '132', '133', '134', '135', '136',
    '137', '138', '139', '140', '141', '142', '143', '144', '145', '146', '147',
    '148', '149', '150', '151', '152', '153', '154', '155', '156', '157', '158',
    '159', '160', '161', '162', '163', '164', '165', '166', '167', '168', '169',
    '170', '171', '172', '173', '174', '175', '176', '177', '178', '179', '180',
    '181', '182', '183', '184', '185', '186', '187', '188', '189', '190', '191',
    '192', '193', '194', '195', '196', '197', '198', '199', '200', '201', '202',
    '203', '204', '205', '206', '207', '208', '209', '210', '211', '212', '213',
    '214', '215', '216', '217', '218', '219', '220', '221', '222', '223', '224',
    '225', '226', '227', '228', '229', '230', '231', '232', '233', '234', '235',
    '236', '237', '238', '239', '240', '241', '242', '243', '244', '245', '246',
    '247', '248', '249', '250', '251', '252', '253', '254', '255', '256', '257',
    '258', '259', '260', '261', '262', '263', '264', '265', '266', '267', '268',
    '269', '270', '271', '272', '273', '274', '275', '276', '277', '278', '279',
    '280', '281', '282', '283', '284', '285', '286', '287', '288', '289', '290',
    '291', '292', '293', '294', '295', '296', '297', '298', '299', '300', '301',
    '302', '303', '304', '305', '306', '307', '308', '309', '310', '311', '312',
    '313', '314', '315', '316', '317', '318', '319', '320', '321', '322', '323',
    '324', '325', '326', '327', '328', '329', '330', '331', '332', '333', '334',
    '335', '336', '337', '338', '339', '340', '341', '342', '343', '344', '345',
    '346', '347', '348', '349', '350', '351', '352', '353', '354', '355', '356',
    '357', '358', '359', '360', '361', '362', '363', '364', '365', '366', '367',
    '368', '369', '370', '371', '372', '373', '374', '375', '376', '377', '378',
    '379', '380', '381', '382', '383', '384', '385', '386', '387', '388', '389',
    '390', '391', '392', '393', '394', '395', '396', '397', '398', '399', '400',
    '401', '402', '403', '404', '405', '406', '407', '408', '409', '410', '411',
    '412', '413', '414', '415', '416', '417', '418', '419', '420', '421', '422',
    '423', '424', '425', '426', '427', '428', '429', '430', '431', '432', '433',
    '434', '435', '436', '437', '438', '439', '440', '441', '442', '443', '444',
    '445', '446', '447', '448', '449', '450', '451', '452', '453', '454', '455',
    '456', '457', '458', '459', '460', '461', '462', '463', '464', '465', '466',
    '467', '468', '469', '470', '471', '472', '473', '474', '475', '476', '477',
    '478', '479', '480', '481', '482', '483', '484', '485', '486', '487', '488',
    '489', '490', '491', '492', '493', '494', '495', '496', '497', '498', '499',
    '500', '501', '502', '503', '504', '505', '506', '507', '508', '509', '510',
    '511']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
bb_pll_is_locked
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
rx_pll_is_locked
- Type: enum
  - Allowed values: ['false', 'true', 'unknown']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
rx_fastlock_delete: Performs a deletion of an RX fastlock profile saved in this worker’s memory. The profile which is deleted is the one whose profile ID matches the value written to this property.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
tx_pll_is_locked
- Type: enum
  - Allowed values: ['false', 'true', 'unknown']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
tx_fastlock_delete: Performs a deletion of an RX fastlock profile saved in this worker’s memory. The profile which is deleted is the one whose profile ID matches the value written to this property.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: None
rx_vco_divider
- Type: enum
  - Allowed values: ['2', '4', '8', '16', '32', '64', '128', 'external_2', 'invalid']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
rx_vco_n_integer
- Type: ushort
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
rx_vco_n_fractional
- Type: ulong
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Rx_Ref_Divider: Rx Ref Divider. This controls the Rx path divider which scales the rate of the analog clock which is input to the Rx PLL Synthesizer (which generates the Rx LO clock). Only possible ratios are: 1, 1/2, 1/4, 2. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal Rx LO frequency value (No-OS does not provide a method for high-precision calculation of the nominal LO frequencies).
- Type: float
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
tx_vco_divider
- Type: enum
  - Allowed values: ['2', '4', '8', '16', '32', '64', '128', 'external_2', 'invalid']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
tx_vco_n_integer
- Type: ushort
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
tx_vco_n_fractional
- Type: ulong
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Tx_Ref_Divider: Tx Ref Divider. This controls the Tx path divider which scales the rate of the analog clock which is input to the Tx PLL Synthesizer (which generates the Tx LO clock). Only possible ratios are: 1, 1/2, 1/4, 2. The purpose of this property is to expose this value as it exists on the AD9361 IC in order to precisely calculate the current on-chip (in-situ) nominal Tx LO frequency value (No-OS does not provide a method for high-precision calculation of the nominal LO frequencies).
- Type: float
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Tx_Channel_Swap: Setting this to true swaps the positions of Tx1 and Tx2 samples.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
Rx_Channel_Swap: Setting this to true swaps the positions of Rx1 and Rx2 samples.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
LVDS: Value is true if bitstream monitored by instance of this worker was built to use LVDS mode for Data/clock/frame signals, and false if CMOS mode was used.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
single_port: Value is true if bitstream monitored by instance of this worker was built to use single port, and false if dual ports.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
swap_ports: Value is true if bitstream monitored by instance of this worker was built to swap Port 0 and Port 1, and false if there was no swap.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
half_duplex: Value is true if bitstream monitored by instance of this worker was built to use half duplex mode, and false if full duplex mode.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
data_rate_config: Value indicates which data rate mode (SDR/DDR) the bitstream was built to use.
- Type: enum
  - Allowed values: ['SDR', 'DDR']
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
DATA_CLK_P_rate_Hz
- Type: double
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
BIST_Mask_Channel_2_Q_data: Setting zeros out Channel 2 Q data.
- Type: bool
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
BIST_Mask_Channel_2_I_data: Setting zeros out Channel 2 I data.
- Type: bool
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
BIST_Mask_Channel_1_Q_data: Setting zeros out Channel 1 Q data.
- Type: bool
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None
BIST_Mask_Channel_1_I_data: Setting zeros out Channel 1 I data.
- Type: bool
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: True
- Default value: None

Ports

Inputs:

None.

Outputs:

None.

Implementations

ad9361_config_proxy (RCC)

Dependencies

The dependencies to other elements in OpenCPI are:

assets/hdl/devices/ad9361_config_proxy.rcc/ad9361_config_proxy.cc

assets/hdl/devices/ad9361_config_proxy.rcc/ad9361_platform.cc

assets/hdl/devices/ad9361_config_proxy.rcc/parameters.h

assets/hdl/devices/ad9361_config_proxy.rcc/supporting/include/OCPIProjects/AD9361ConfigProxy.hh

assets/hdl/devices/ad9361_config_proxy.rcc/supporting/include/OCPIProjects/LogForwarder.hh

assets/hdl/devices/ad9361_config_proxy.rcc/supporting/src/OCPIProjects/AD9361ConfigProxy.cc

assets/hdl/devices/ad9361_config_proxy.rcc/supporting/src/OCPIProjects/LogForwarder.cc

Limitations

Limitations of ad9361_config_proxy are:

None.

Testing

Tested platforms include Agilent ZedBoard/Analog Devices FMCOMMS2 (xilinx24_1_aarch32 RCC platform), Ettus E310 (xilinx24_1_aarch32 RCC platform).

The test outlined in Ad9361 dac (ad9361_dac) includes validation of a subset of this worker’s functionality.

Troubleshooting

The following error message, which is produced by the Analog Device’s No-OS software library utilized by ad9361 config proxy.rcc, indicates a hardware communication error between the FPGA and the AD9361. This message would occur, for example, if the AD9361 existed on a card which was not plugged in to the PCB containing the FPGA.

ad9361_init : Unsupported PRODUCT_ID 0xC0ad9361_init : AD936x initialization error

References

Analog Device’s No-OS software library

AD9361 IC

Ad9361 dac (ad9361_dac)

Ad9361 config proxy (ad9361_config_proxy)

Design

Interface

Properties

Ports

Implementations

Dependencies

Limitations

Testing

Troubleshooting

References

Ad9361 config proxy (`ad9361_config_proxy`)