Ad9361 dac (ad9361_dac)

Design

The AD9361 DAC device worker ingests a single TX channel’s data to be sent to the AD9361 IC. Up to two instances of this worker can be used to send multichannel TX data to an AD9361 in an independent, non-phase-coherent fashion. This worker also has a port which controls AD9361 transmitter power on/off.

A block diagram representation of the implementation is given in Figure 182:

ad9361_dac block diagram.

Figure 182: ad9361_dac block diagram.

Interface

<!-- AD9361 DAC worker -->
<HdlDevice language="vhdl" spec='qdac' version='2'
  ExactParts="
    zynq:xc7z020-1-clg484
    zynq_ise:xc7z020_ise_alias-1-clg484
    zynq_ultra:xczu7ev-2-ffvc1156e
    virtex6:xc6vlx240t-1-ff1156
    stratix4:ep4sgx230k-c2-f40
    artix7:xc7a50t-2-csg325"
  SourceFiles="trunc_round_16_to_12_signed.vhd"
  Libraries="platform misc_prims">
  <!-- Properties -->
  <Property name='fifo_depth' type='ulong' parameter='1' default='64' description='Depth in number of samples of the control-to-DAC clock domain crossing FIFO.'/> <!-- default depth of 64 has been tested and known to be valid -->
  <Property Name="IDATA_WIDTH_p" Type="ushort" Default="32" Parameter="true"/>

  <!-- min_num_cp_clks_per_txen_event default value calculation:
       min AD9361 LVDS sample rate (pre-FIR) = 50e6/24 ~= 2.083333 MHz
       max AD9361 TX Fir interpolation factor = 4
       LVDS num clocks / sample = 2 (1R1T) or 4 (2R2T)
       LVDS min num clocks / sample = 2
       min LVDS sample rate = (min LVDS sample rate / max interpolation factor) ~= 520.833 kHz
       min FBCLK rate = min LVDS sample rate * (LVDS min num clocks/sample) ~= 1.041667 MHz
       fastest known control plane clock = 125 MHz (ml605)
       min_num_cp_clks_per_txen_event = ceil(1.5 * CP clk / (min FBCLK rate))
                                      = ceil(1.5*125e6/(1.041666e6))
                                      = ceil(180) = 180
  -->
  <Property name='min_num_cp_clks_per_txen_event' type='ushort' initial='true' default='180' description='After every ZLM received on the event_in port, backpressure will be held on that port for one less than the number of control plane clock cycles specified by this property. This is done in order to ensure tx events are properly synchronized to the AD9361 FB_CLK without losing any events. Minimum required value is ceil(1.5 * control plane clock rate / AD9361 FB_CLK rate [use lowest expected FB_CLK rate for your scenario]).'/>
  <!-- Ports -->
  <StreamInterface Name="in" DataWidth="IDATA_WIDTH_p" Optional="1" maxmessagevalues='8192'/>
  <StreamInterface Name="event_in" Optional="1" ZeroLengthMessages="true"/>

  <devsignal name='dev_dac' signals='dac-12-signals.xml' master='true'/>

  <devsignal name='dev_tx_event' signals='ad9361-tx-event-signals.xml' master='true'/>
</HdlDevice>

Implementations

Dependencies

The dependencies to other elements in OpenCPI are:

  • core/hdl/primitives/util/util_pkg.vhd

  • core/hdl/primitives/util/zlm_detector.vhd

  • assets/hdl/devices/ad9361_dac.hdl/ad9361_dac.vhd

  • assets/hdl/devices/ad9361_dac.hdl/trunc_round_16_to_12_signed.vhd

  • assets/hdl/primitives/misc_prims/event_in_to_txen/src/event_in_to_txen.vhd

  • assets/hdl/primitives/misc_prims/misc_prims_pkg.vhd

  • assets/hdl/primitives/util/dac_fifo.vhd

  • assets/hdl/primitives/util/util_pkg.vhd

  • assets/hdl/primitives/util/sync_status.vhd

  • assets/hdl/primitives/bsv/imports/SyncFIFO.v

  • assets/hdl/primitives/bsv/imports/SyncResetA.v

  • assets/hdl/primitives/bsv/imports/SyncHandshake.v

  • assets/hdl/primitives/bsv/bsv_pkg.vhd

Limitations

Limitations of ad9361_dac are:

  • None.

Testing

Tested platforms include Agilent Zedboard/Analog Devices FMCOMMS2 (Vivado only), Agilent Zedboard/Analog Devices FMCOMMS3 (Vivado only), Ettus E310 (Vivado only, application for testing exists in e310 project).

No test yet exists for this component.

Appendix

Vivado timing analysis details for ad9361_dac are documented in Appendix.

References