Appendix
Appendix - Vivado Timing Analysis
The Vivado timing report that OpenCPI runs for device workers may erroneously report a max delay for a clocking path which should have been ignored. Custom Vivado tcl commands had to be run for this device worker to extract pertinent information from Vivado timing analysis. After building the worker, the following commands were run from the assets project directory (after the Vivado settings64.sh was sourced):
cd hdl/devices/
vivado -mode tcl
Then the following commands were run inside the Vivado tcl terminal. Note this example is for build configuration 0 only.
open_project ad9361_adc_sub.hdl/target-zynq/ad9361_adc_sub_rv.xpr
synth_design -part xc7z020clg484-1 -top ad9361_adc_sub_rv -mode out_of_context
create_clock -name clk1 -period 0.001 [get_nets {ctl_in[Clk]}]
create_clock -name clk2 -period 0.001 [get_nets {dev_data_clk_in[DATA_CLK_P]}]
set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2]
report_timing -delay_type min_max -sort_by slack -input_pins -group clk1
report_timing -delay_type min_max -sort_by slack -input_pins -group clk2
The following is the output of the timing reports. The Fmax for the control plane clock for this worker is computed as the maximum magnitude slack with a control plane clock of 1 ps plus 2 times the assumed 1 ps control plane clock period (3.172 ns + 0.002 ns = 3.174 ns, 1/3.174 ns = 315.06 MHz). The Fmax for the dev_data_clk clock from the devsignal is computed as the maximum magnitude slack with dev_data_clk of 1 ps plus 2 times the assumed 1 ps dev_data_clk period (2.387 ns + 0.002 ns = 2.389 ns, 1/2.389 ns = 418.59 MHz).
Vivado% report_timing -delay_type min_max -sort_by slack -input_pins -group clk1
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port ``ctl_in[Clk]'' is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port ``dev_data_clk_in[DATA_CLK_P]'' is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type min_max -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.1 (lin64) Build 1846317 Fri Apr 14 18:54:47 MDT 2017
| Date : Mon Oct 1 14:28:58 2018
| Host : <removed> running 64-bit CentOS Linux release 7.5.1804 (Core)
| Command : report_timing -delay_type min_max -sort_by slack -input_pins -group clk1
| Design : ad9361_adc_sub_rv
| Device : 7z020-clg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
-------------------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -3.172ns (required time - arrival time)
Source: wci/wci_decode/my_state_r_reg[2]/C
(rising edge-triggered cell FDRE clocked by clk1 {rise@0.000ns fall@0.001ns period=0.001ns})
Destination: wci/wci_decode/FSM_onehot_my_access_r_reg[0]/CE
(rising edge-triggered cell FDSE clocked by clk1 {rise@0.000ns fall@0.001ns period=0.001ns})
Path Group: clk1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 0.002ns (clk1 rise@0.002ns - clk1 rise@0.000ns)
Data Path Delay: 2.921ns (logic 0.937ns (32.078%) route 1.984ns (67.922%))
Logic Levels: 2 (LUT6=2)
Clock Path Skew: -0.049ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.924ns = ( 0.926 - 0.002 )
Source Clock Delay (SCD): 0.973ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk1 rise edge) 0.000 0.000 r
0.000 0.000 r ctl_in[Clk] (IN)
net (fo=41, unset) 0.973 0.973 wci/wci_decode/ctl_in[Clk]
FDRE r wci/wci_decode/my_state_r_reg[2]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.518 1.491 r wci/wci_decode/my_state_r_reg[2]/Q
net (fo=7, unplaced) 1.000 2.491 wci/wci_decode/wci_state[2]
r wci/wci_decode/ctl_out[SResp][1]_INST_0_i_2/I0
LUT6 (Prop_lut6_I0_O) 0.295 2.786 r wci/wci_decode/ctl_out[SResp][1]_INST_0_i_2/O
net (fo=4, unplaced) 0.473 3.259 wci/wci_decode/ctl_out[SResp][1]_INST_0_i_2_n_0
r wci/wci_decode/FSM_onehot_my_access_r[4]_i_2/I2
LUT6 (Prop_lut6_I2_O) 0.124 3.383 r wci/wci_decode/FSM_onehot_my_access_r[4]_i_2/O
net (fo=8, unplaced) 0.511 3.894 wci/wci_decode/my_access_r
FDSE r wci/wci_decode/FSM_onehot_my_access_r_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk1 rise edge) 0.002 0.002 r
0.000 0.002 r ctl_in[Clk] (IN)
net (fo=41, unset) 0.924 0.926 wci/wci_decode/ctl_in[Clk]
FDSE r wci/wci_decode/FSM_onehot_my_access_r_reg[0]/C
clock pessimism 0.000 0.926
clock uncertainty -0.035 0.891
FDSE (Setup_fdse_C_CE) -0.169 0.722 wci/wci_decode/FSM_onehot_my_access_r_reg[0]
-------------------------------------------------------------------
required time 0.722
arrival time -3.894
-------------------------------------------------------------------
slack -3.172
report_timing: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2089.160 ; gain = 497.523 ; free physical = 604 ; free virtual = 55948
Vivado% report_timing -delay_type min_max -sort_by slack -input_pins -group clk2
Timing Report
Slack (VIOLATED) : -2.387ns (required time - arrival time)
Source: worker/data_mode_lvds.rx_frame_p_ddr/C
(rising edge-triggered cell IDDR clocked by clk2 {rise@0.000ns fall@0.001ns period=0.001ns})
Destination: worker/data_mode_lvds.adc_r1_i_h_rrr_reg[0]/CE
(rising edge-triggered cell FDRE clocked by clk2 {rise@0.000ns fall@0.001ns period=0.001ns})
Path Group: clk2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 0.002ns (clk2 rise@0.002ns - clk2 rise@0.000ns)
Data Path Delay: 2.007ns (logic 0.686ns (34.185%) route 1.321ns (65.815%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.849ns = ( 1.851 - 0.002 )
Source Clock Delay (SCD): 2.094ns
Clock Pessimism Removal (CPR): 0.099ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk2 rise edge) 0.000 0.000 r
0.000 0.000 r dev_data_clk_in[DATA_CLK_P] (IN)
net (fo=0) 0.973 0.973 worker/dev_data_clk_in[DATA_CLK_P]
r worker/BUFR_inst/I
BUFR (Prop_bufr_I_O) 0.537 1.510 r worker/BUFR_inst/O
net (fo=140, unplaced) 0.584 2.094 worker/dev_data_ch0_out_out[adc_clk]
IDDR r worker/data_mode_lvds.rx_frame_p_ddr/C
------------------------------------------------------------------- -------------------
IDDR (Prop_iddr_C_Q2) 0.508 2.602 r worker/data_mode_lvds.rx_frame_p_ddr/Q2
net (fo=3, unplaced) 0.800 3.401 worker/adc_rx_frame_p_buf_rr13_out
r worker/adc_r1_i_h_rrr/I0
LUT3 (Prop_lut3_I0_O) 0.178 3.579 r worker/adc_r1_i_h_rrr/O
net (fo=12, unplaced) 0.521 4.100 worker/adc_r1_q_h_rrr_0
FDRE r worker/data_mode_lvds.adc_r1_i_h_rrr_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk2 rise edge) 0.002 0.002 r
0.000 0.002 r dev_data_clk_in[DATA_CLK_P] (IN)
net (fo=0) 0.924 0.926 worker/dev_data_clk_in[DATA_CLK_P]
r worker/BUFR_inst/I
BUFR (Prop_bufr_I_O) 0.486 1.412 r worker/BUFR_inst/O
net (fo=140, unplaced) 0.439 1.851 worker/dev_data_ch0_out_out[adc_clk]
FDRE r worker/data_mode_lvds.adc_r1_i_h_rrr_reg[0]/C
clock pessimism 0.099 1.951
clock uncertainty -0.035 1.915
FDRE (Setup_fdre_C_CE) -0.202 1.713 worker/data_mode_lvds.adc_r1_i_h_rrr_reg[0]
-------------------------------------------------------------------
required time 1.713
arrival time -4.100
-------------------------------------------------------------------
slack -2.387
These calculations can be verified by replacing the create_clock lines above with the following values and rerunning the report_timing commands and observing a value of 0.000 ns for the slacks:
create_clock -name clk1 -period 3.174 [get_nets {ctl_in[Clk]}]
create_clock -name clk2 -period 2.389 [get_nets {dev_data_clk_in[DATA_CLK_P]}]
report_timing -delay_type min_max -sort_by slack -input_pins -group clk1
report_timing -delay_type min_max -sort_by slack -input_pins -group clk2
For the clk2 example:
Vivado% report_timing -delay_type min_max -sort_by slack -input_pins -group clk2
Timing Report
Slack (MET) : 0.000ns (required time - arrival time)
Source: worker/data_mode_lvds.rx_frame_p_ddr/C
(rising edge-triggered cell IDDR clocked by clk2 {rise@0.000ns fall@1.194ns period=2.389ns})
Destination: worker/data_mode_lvds.adc_r1_i_h_rrr_reg[0]/CE
(rising edge-triggered cell FDRE clocked by clk2 {rise@0.000ns fall@1.194ns period=2.389ns})
Path Group: clk2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.389ns (clk2 rise@2.389ns - clk2 rise@0.000ns)
Data Path Delay: 2.007ns (logic 0.686ns (34.185%) route 1.321ns (65.815%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.849ns = ( 4.238 - 2.389 )
Source Clock Delay (SCD): 2.094ns
Clock Pessimism Removal (CPR): 0.099ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk2 rise edge) 0.000 0.000 r
0.000 0.000 r dev_data_clk_in[DATA_CLK_P] (IN)
net (fo=0) 0.973 0.973 worker/dev_data_clk_in[DATA_CLK_P]
r worker/BUFR_inst/I
BUFR (Prop_bufr_I_O) 0.537 1.510 r worker/BUFR_inst/O
net (fo=140, unplaced) 0.584 2.094 worker/dev_data_ch0_out_out[adc_clk]
IDDR r worker/data_mode_lvds.rx_frame_p_ddr/C
------------------------------------------------------------------- -------------------
IDDR (Prop_iddr_C_Q2) 0.508 2.602 r worker/data_mode_lvds.rx_frame_p_ddr/Q2
net (fo=3, unplaced) 0.800 3.401 worker/adc_rx_frame_p_buf_rr13_out
r worker/adc_r1_i_h_rrr/I0
LUT3 (Prop_lut3_I0_O) 0.178 3.579 r worker/adc_r1_i_h_rrr/O
net (fo=12, unplaced) 0.521 4.100 worker/adc_r1_q_h_rrr_0
FDRE r worker/data_mode_lvds.adc_r1_i_h_rrr_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk2 rise edge) 2.389 2.389 r
0.000 2.389 r dev_data_clk_in[DATA_CLK_P] (IN)
net (fo=0) 0.924 3.313 worker/dev_data_clk_in[DATA_CLK_P]
r worker/BUFR_inst/I
BUFR (Prop_bufr_I_O) 0.486 3.799 r worker/BUFR_inst/O
net (fo=140, unplaced) 0.439 4.238 worker/dev_data_ch0_out_out[adc_clk]
FDRE r worker/data_mode_lvds.adc_r1_i_h_rrr_reg[0]/C
clock pessimism 0.099 4.338
clock uncertainty -0.035 4.302
FDRE (Setup_fdre_C_CE) -0.202 4.100 worker/data_mode_lvds.adc_r1_i_h_rrr_reg[0]
-------------------------------------------------------------------
required time 4.100
arrival time -4.100
-------------------------------------------------------------------
slack 0.000