Ad9361 adc (ad9361_adc)

Design

The AD9361 ADC device worker outputs a single RX channel’s data from the AD9361 IC via an iqstream output port. Up to two instances of this worker can be used to provide each AD9361 RX channel data stream in an independent, non-phase-coherent fashion.

A block diagram representation of the implementation is given in Figure 179:

ad9361_adc block diagram.

Figure 179: ad9361_adc block diagram.

Interface

<!-- AD9361 ADC worker -->
<HdlDevice language="vhdl" spec='qadc' Libraries="platform"
  ExactParts="
    zynq:xc7z020-1-clg484
    zynq_ise:xc7z020_ise_alias-1-clg484
    zynq_ultra:xczu7ev-2-ffvc1156e
    virtex6:xc6vlx240t-1-ff1156
    stratix4:ep4sgx230k-c2-f40
    artix7:xc7a50t-2-csg325">

  <!-- Properties -->
  <Specproperty name='messageSize' default='8192'/>
  <Specproperty name='overrun' default='0'/>
  <Property name='fifo_depth' type='ulong' parameter='1' default='64'
	    description='Clock domain crossing FIFO depth in samples.'/>
  <!--Property name='overrange' type='bool' volatile='1' writable='1' description='This property reads the value of a sticky bit internal to the HDL device which goes high once the maximum amplitude ADC value (on high or low side) is read, indicating that clipping occured at the ADC sample boundary. Writing false will clear the sticky bit.'/--> <!-- TODO / FIXME - add overrange -->

  <!-- Ports -->
  <StreamInterface Name="OUT" producer='true' DataWidth="32"/>

  <devsignal name='dev_adc' signals='adc-12-signals.xml' master='true'/>
</HdlDevice>

Implementations

Dependencies

The dependencies to other elements in OpenCPI are:

  • assets/hdl/devices/ad9361_adc.hdl/ad9361_adc.vhd

  • core/hdl/primitives/util/adc_fifo.vhd

  • core/hdl/primitives/util/sync_status.vhd

  • core/hdl/primitives/util/util_pkg.vhd

  • core/hdl/primitives/bsv/imports/SyncFIFO.v

  • core/hdl/primitives/bsv/imports/SyncResetA.v

  • core/hdl/primitives/bsv/imports/SyncHandshake.v

  • core/hdl/primitives/bsv/bsv_pkg.vhd

Limitations

Limitations of ad9361_adc are:

  • None.

Testing

Tested platforms include Agilent Zedboard/Analog Devices FMCOMMS2 (Vivado only), Agilent Zedboard/Analog Devices FMCOMMS3 (Vivado only), Ettus E310 (Vivado only, application for testing exists in e310 project).

No unit test for this component exists. However, a hardware-in-the-loop application (which is NOT a unit test) exists for testing purposes (see assets/applications/ad9361_adc_test).

Appendix

Verification (data fidelity / delay setting) and Vivado timing analysis details for ad9361_adc are documented in Appendix.

References