Si5351 (si5351)
Design
The SI5351 device worker exposes the register set of the Si5351C I2C clock generator IC and directly interfaces with the IC’s INTR and EOB pins. Each register is exposed as a uchar (8-bits wide) property. The worker drives the EOB pin to ground and the INTR pin’s signal is currently unused. The Si5351C SDA/SCL pins are not controlled directly by this worker, but instead by a subdevice of this worker which arbitrates I2C bus access.
Interface
<!-- device worker for Si5351C I2C-Programmable Clock Generator IC-->
<!-- __________________________________________________________ -->
<!-- | FPGA | -->
<!-- | (represented by /\ | -->
<!-- | OpenCPI platform) | control plane interface exposes | -->
<!-- | | each Si5351C register as a | -->
<!-- | _______V_____ uchar property | -->
<!-- | ______________|_______|_____|__ | -->
<!-- || si5351.hdl | | (other device | -->
<!-- ||______________________|________| workers on | -->
<!-- | /\intr |oeb |_______|_____| I2C bus.....) | -->
<!-- | | | /\ /\ /\ | -->
<!-- | | | raw property| ........................: : | -->
<!-- | | | interface| : ............................: | -->
<!-- | | | ____V_:_:_ | -->
<!-- | | | _______|____|_:_:_|___ | -->
<!-- | | | | <>_i2c.hdl | : : | worker/platform/card- | -->
<!-- | | | | __________|_:_:___ | specific subdevice | -->
<!-- | | | | | raw prop arbiter | | worker which arbitrates| -->
<!-- | | | | |__________________| | I2C bus access | -->
<!-- | | | |_______|_____|________| | -->
<!-- | | | /\ /\ | -->
<!-- | | | | | I2C bus signals | -->
<!-- |_|______V_________V_____V_________________________________| -->
<!-- | | |.....|... (other -->
<!-- | | | |... IC devices) -->
<!-- _|______|_________|_____|_________________________________ -->
<!-- |INTR OEB SDA SCL | -->
<!-- | Si5351C IC | -->
<!-- |__________________________________________________________| -->
<!-- -->
<HdlDevice language='vhdl' FirstRawProperty='dev_status'>
<ComponentSpec/>
<!-- I2C read/write transactions require additional time to complete -->
<ControlInterface Timeout='131072'/>
<!-- ==============================================================
Annotations of this device worker, settable by the platform, available to proxy
============================================================== -->
<!-- Does this chip have an external clock as input? -->
<property name='clkin_present' type='bool' parameter='1' default='0'/>
<property name='clkin_freq' type='float' parameter='1' default='0'/>
<!-- Does this chip have a crystal oscillator as input? -->
<property name='xtal_present' type='bool' parameter='1' default='0'/>
<property name='xtal_freq' type='float' parameter='1' default='0'/>
<!-- Does this chip have a VCXO as input? -->
<property name='vc_present' type='bool' parameter='1' default='0'/>
<property name='outputs_present' type='bool' arraylength='8' parameter='1' default='0'/>
<property name='oeb_mode' type='enum' parameter='1' enums='low,high,connected' default='low'/>
<property name='intr_connected' type='bool' parameter='1' default='0'/>
<!-- ==============================================================
Hardware registers in this chip
============================================================== -->
<!--Device Status -->
<property name='dev_status' type='uchar'/> <!-- 0 -->
<!--Interrupt Status Sticky -->
<property name='int_sts_stcky' type='uchar' volatile='true' writable='true'/> <!-- 1 -->
<!--Interrupt Status Mask -->
<property name='int_sts_mask' type='uchar' writable='true'/> <!-- 2 -->
<!--Output enable control -->
<property name='out_en_ctl' type='uchar' writable='true'/> <!-- 3 -->
<!--Reserved -->
<property name='reserved00' type='uchar' padding='1' arraylength='5'/> <!-- 4-8 -->
<!--OEB pin enable control mask -->
<property name='oeb_pin_en' type='uchar' volatile='true' writable='true'/> <!-- 9 -->
<!--Reserved -->
<property name='reserved01' type='uchar' padding='1' arraylength='5'/> <!-- 10-14 -->
<!--PLL Input Source -->
<property name='pll_in_src' type='uchar' writable='true'/> <!-- 15 -->
<!--Clock Control -->
<property name='clk_ctl' type='uchar' writable='true' arraylength='8'/> <!-- 16 - 23 -->
<!--Clock Disable State -->
<property name='clk30_dis_st' type='uchar' volatile='true' writable='true'/> <!-- 24 -->
<property name='clk74_dis_st' type='uchar' volatile='true' writable='true'/> <!-- 25 -->
<!-- Feedback Multisynth Divider Parameters (doc section 3.2) - one set per PLL (NOT per MS output) -->
<property name='ms_div_params' type='uchar' writable='true' arraydimensions='2,8'/> <!-- 26 - 41 -->
<!-- Output Multisynth Parameters (doc section 4.1) - one set of 8 regs per MS output for the first 6 -->
<property name='ms_0_5_params' type='uchar' writable='true' arraydimensions='6,8'/> <!-- 42 - 89 -->
<!-- Output Multisynth Parameters (doc section 4.1) - one register per MS output for the last 2 -->
<property name='ms_6_7_params' type='uchar' writable='true' arraylength='2'/> <!-- 90 - 91 -->
<!--Clock 6-7 Output divider -->
<property name='clk67_div' type='uchar' writable='true'/> <!-- 92 -->
<!--Padding -->
<property name='pad0' type='uchar' padding='true' arraylength='56'/> <!-- 93 - 148 -->
<!--Spread Spectrum Parameters -->
<property name='ss_params' type='uchar' writable='true' arraylength='13'/> <!-- 149 - 161 -->
<!--VCXO Parameters -->
<property name='vcx' type='uchar' writable='true' arraylength='3'/> <!-- 162 - 164 -->
<!--Initial Phase Offsets -->
<property name='clk_phs_offs' type='uchar' writable='true' arraylength='6'/> <!-- 165 - 170 -->
<!--Reserved -->
<property name='reserved02' type='uchar' padding='true' arraylength='6'/> <!-- 171 - 176-->
<!--PLL Reset -->
<property name='pll_reset' type='uchar' writable='true'/> <!-- 177 -->
<!--Reserved -->
<property name='reserved16' type='uchar' padding='true' arraylength='5'/> <!-- 178-182 -->
<!--Crystal Internal Load Capacitance -->
<property name='xtal_cl' type='uchar' writable='true'/> <!-- 183 -->
<!--Reserved -->
<property name='reserved03' type='uchar' padding='true' arraylength='3'/> <!-- 184-186 -->
<!--Fanout enable -->
<property name='fanout_en' type='uchar' writable='true'/> <!-- 187 -->
<!--Reserved -->
<property name='reserved04' type='uchar' padding='true' arraylength='68'/> <!-- 188-255 -->
<!--Need these signals to control i2c_opencores -->
<rawprop name='rawprops' master='true'/>
<!-- Interrupt indication, when connected -->
<signal input='intr'/>
<!-- master output enable of all clock outputs, asserted LOW. Disabled by reg 9 -->
<signal output='oeb'/>
</HdlDevice>
Implementations
si5351(HDL)
Dependencies
The dependencies to other elements in OpenCPI are:
assets/hdl/devices/si5351.hdl/si5351.vhd
Limitations
Limitations of si5351 are:
None.
Testing
Tested platforms include zed/Zipper.