ad9361_spi HDL Worker

Detail

The ad9361_spi.hdl subdevice worker is intend for use in platforms/cards where a SPI bus exists which addresses only the AD9361. SPI read/writes are actuated by the rprops rawprop port. A devsignal is also sent which can force the AD9361 RESETB pin, which is active-low, to logic 0.

Control Timing and Signals

The AD9361 SPI.hdl device worker operates entirely in the control plane clock domain. All SPI data and SPI clock signals are generated in the control plane clock domain. Note that SPI clock can only be a divided version of the control plane clock.

Performance and Resource Utilization

Fmax refers to the maximum allowable clock rate for any registered signal paths within a given clock domain for an FPGA design. Fmax in the table below is specific only to this worker and represents the maximum possible Fmax for any OpenCPI bitstream built with this worker included. Note that the Fmax value for a given clock domain for the final bitstream is often worse than the Fmax specific to this worker, even if this worker is the only one included in the bitstream.

Table 114: Resource Utilization Table for worker: ad9361_spi

Configuration

OCPI Target

Tool

Version

Device

Registers (Typ)

LUTs (Typ)

Fmax (MHz) (Typ)

Memory/Special Functions

0

zynq

Vivado

2017.1

xc7z020clg484-1

67

94

235 1

N/A

0

stratix4

Quartus

17.1.0

EP4SGX230KF40C2

70

139

N/A

N/A

0

virtex6

ISE

14.7

6vlx240tff1156-1

65

130

437.445

N/A

1

zynq

Vivado

2017.1

xc7z020clg484-1

68

101

315 1

N/A

1

stratix4

Quartus

17.1.0

EP4SGX230KF40C2

71

141

N/A

N/A

1

virtex6

ISE

14.7

6vlx240tff1156-1

65

134

412.712

N/A
1(1,2)

These measurements were the result of a Vivado timing analysis which was different from the Vivado analysis performed by default for OpenCPI worker builds. For more info see Appendix.

Worker Properties

  • CP_CLK_FREQ_HZ_p

    • Type: float

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • SPI_CLK_FREQ_HZ_p

    • Type: float

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • lastAddr

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • lastData

    • Type: uchar

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • resetting

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

Worker Ports

    Interfaces (other than data I/O ports):

  • dev_force_reset

    • Type: devsignal

  • rprops

    • Type: rawprop

    • Subdevice Connections:

    • Supported device worker: ad9361_config


      Connections:


      • Subdevice port: rawprops

      • Supported worker port: rprops

        • Index: None


      • Subdevice port: dev_force_spi_reset

      • Supported worker port: dev_force_reset

        • Index: None


Worker Signals

  • force_reset

    • Direction: out

    • Differential: false

    • Pin: false

  • SPI_DI

    • Direction: out

    • Differential: false

    • Pin: false

  • SPI_CLK

    • Direction: out

    • Differential: false

    • Pin: false

  • SPI_ENB

    • Direction: out

    • Differential: false

    • Pin: false

  • SPI_DO

    • Direction: in

    • Differential: false

    • Pin: false

  • RESETB

    • Direction: out

    • Differential: false

    • Pin: false

Utilization

Utilization reporting is not currently implemented.

References