ad9361_dac_sub HDL Worker

Detail

The ad9361_dac_sub.hdl subdevice worker handles registering and interleaving of two independent TX data streams which are sent to this worker via the dev_data_ch0_in and dev_data_ch1_in devsignal ports. Data is sent out via the dev_data_to_pins devsignal port which ad9361_data_sub.hdl routes to the AD9361:ref:ad9361_data_sub. This worker’s LVDS_p, HALF_DUPLEX_p, SINGLE_PORT_p, and DATA_RATE_CONFIG_p parameter properties enforce build-time configuration for all of the possible AD9361 TX data time-interleaved modes. The currently supported modes and their limitations are shown in the following table.

Table 111: Supported DAC Sampling Rates per TX channel

Platform/Cards which

AD9361 Data Port Mode

AD9361 Channel Mode

Max AD9361-

Max

allow the AD9361

Supported Sampling

ad9361_dac_sub.hdl-

Data Port/Channel

Rate per TX channel

Supported Sampling

Mode

Rate per TX channel

E310

CMOS Single Port Half Duplex SDR

not yet supported

E310

CMOS Single Port Half Duplex DDR

not yet supported

E310

CMOS Single Port Full Duplex SDR

not yet supported

E310

CMOS Single Port Full Duplex DDR

not yet supported

E310

CMOS Dual Port Half Duplex SDR

not yet supported

E310

CMOS Dual Port Half Duplex DDR

not yet supported

E310

CMOS Dual Port Full Duplex SDR

not yet supported

E310

CMOS Dual Port Full Duplex DDR

not yet supported

E310

CMOS Single Port Full Duplex DDR

1R1T, 2R2T Timing=0

30.72 Msps

30.72 Msps

E310

CMOS Single Port Full Duplex DDR

1R1T, 2R2T Timing=1, 2R1T, 1R2T

15.36 Msps

15.36 Msps

FMCOMMS2/3

LVDS (Dual Port Full Duplex DDR)

all configs

61.44 Msps

61.44 Msps (There are limited guarantees of data fidelity on the FMCOMMS2/3 cards for certain multichannel modes on certain platforms, although tests at room temperature have always yielded 100% fidelity.)

Note that “channel 0” within the context of this worker corresponds to the AD9361 T1 channel and “channel 1” corresponds to the AD9361 T2 channel in the AD9361 timing diagrams . The mapping between the AD9361’s T1/T2 channels and the AD9361 physical TX connector outputs is variable depending on the AD9361 register configuration. This relationship is shown in the following table. Due to the AD9361’s T2 behavior , channel 1 should only ever be used when 2 TX channels are desired.

Table 112: Channel Connectivity (D.C. means Don’t Care.)

ad9361_dac_sub.hdl devsignal channel

AD9361 timing diagram

AD9361 TX RF Port

AD9361 Register 0x010 Bit D5 (channel swap)

AD9361 Register 0x002 Bits [D7 D6] (channel enable)

AD9361 Register 0x004 Bit D6 (port select)

0

T1

TX1A

0

[D.C. 1]

0

0

T1

TX1B

0

[D.C. 1]

1

0

T1

TX2A

1

[1 D.C.]

0

0

T1

TX2B

1

[1 D.C.]

1

1

T2

TX2A

0

[1 1]

0

1

T2

TX2B

0

[1 1]

1

1

T2

TX1A

1

[1 1]

0

1

T2

TX1B

1

[1 1]

1

Control Timing and Signals

The AD9361 DAC Sub subdevice worker contains four clock domains: control plane, FB_CLK_P, “dac_clk” and “dacd2_clk”.

Control Plane Clock Domain

The data_cfg_tx signals enter this worker in the control plane clock domain. Inside this worker, they are combined combinatorially into a single signal which is subsequently synchronized to the dacd2_clk domain. The dacd2_clk domain signal is then used to handle time-interleaving of multiple channel’s data.

DATA CLK P/FB CLK P Clock Domain

The AD9361 DATA_CLK_P clock enters this worker via the dev_data_clk devsignal. DATA_CLK_P clock is forwarded to the FB_CLK_P device signal as well as used to generate dac_clk.

“dac clk” Clock Domain

The “dac_clk” clock is an inverted version of DATA_CLK_P. Note that data transitions for the TX data sent out via the dev_data_to_pins devsignal port are falling-edge aligned with FB_CLK_P since the falling edge is what the AD9361 datasheets specifies its setup/hold requirements against. The dac_clk domain allows for logic within this worker to be falling edge aligned with FB_CLK_P.

“dacd2 clk” Clock Domain

The “dacd2_clk” clock is a divided by 2 version of “dac_clk”. TX data for channel 0 and channel 1 enter this worker in the dacd2_clk domain from the dev_data_ch0_in and dev_data_ch1_in devsignal ports, respectively. The dacd2_clk clock was a necessary replacement for some of the dac_clk logic in order to alleviate timing violations in the dac_clk domain for the zed_ise platform. Note that because dacd2_clk is a divided version of dac_clk, synchronization logic between the two is not necessary and not included.

Data latency

  • LVDS mode and CMOS Single Port Full Duplex

    • Latency for these modes is given as the number of clock cycles from a given channel’s data becoming ready on the dac_data_I and dac_data_Q devsignals to the starting edge of the high 6-bit I word on the AD9361 data bus output. Note that, for multichannel modes, latency can be two possible values depending on the current state of the 2-state channel serialization state machine when dac_data_I/dac_data_Q becomes ready. The latency for the various LVDS and CMOS Single Port Full Duplex configurations are as follows:

    • 1R1T

      • channel 0 data latency = 3 FB_CLK_P cycles (2 are pipeline delay which are arguably unnecessary and 1 is a 12-bit word to 6-bit word serialization register)

    • 2R1T/1R2T/2R2T

      • channel 0 data latency = 3 or 5 FB_CLK_P cycles (2 are pipeline delay which are arguably unnecessary, 2 are possible channel serialization register delay, and 1 is a 12-bit word to 6-bit word serialization register)

      • channel 1 data latency = 3 or 5 FB_CLK_P cycles (2 are pipeline delay which are arguably unnecessary, 2 are possible channel serialization register delay, and 1 is a 12-bit word to 6-bit word serialization register)

Multichannel Phase Coherency

Note that the two channel data made available via dev_data_ch0_in and dev_data_ch1_in are only ever considered to be phase coherent if coherency is guaranteed by the worker(s) that dev_data_ch0_in and dev_data_ch1_in are connected to. For example, multiple instances of ad9361_dac.hdl would not guarantee phase coherence because their datastreams would be independent. However, if a single device worker was created which interfaced with both dev_data_ch0_in and dev_data_ch1_in, phase coherency could be guaranteed by updating the values for the two channels in an every-other-clock fashion.

Performance and Resource Utilization

Fmax refers to the maximum allowable clock rate for any registered signal paths within a given clock domain for an FPGA design. Fmax in the table below is specific only to this worker and represents the maximum possible Fmax for any OpenCPI bitstream built with this worker included. Note that the Fmax value for a given clock domain for the final bitstream is often worse than the Fmax specific to this worker, even if this worker is the only one included in the bitstream.

Table 113: Resource Utilization Table for worker: ad9361_dac_sub

Configuration

OCPI Target

Tool

Version

Device

Registers (Typ)

LUTs (Typ)

Fmax (MHz) (Typ) control plane clock

Fmax (MHz) (Typ) dev_data_clk clock

Memory/Special Functions

0

zynq

Vivado

2017.1

xc7z020clg484-1

94

89

477 1

267 1

ODDR: 7 BUFR: 1

0

virtex6

ISE

14.7

6vlx240tff1156-1

101

113

689.655

632.511

ODDR: 7 BUFR: 1

1

zynq

Vivado

2017.1

xc7z020clg484-1

24

36

477 1

297 1

ODDR: 7

1

virtex6

ISE

14.7

6vlx240tff1156-1

29

44

689.655

496.416

ODDR: 7
1(1,2,3,4)

These measurements were the result of a Vivado timing analysis which was different from the Vivado analysis performed by default for OpenCPI worker builds. For more info see Appendix.

Worker Properties

  • LVDS_p

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • HALF_DUPLEX_p

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • SINGLE_PORT_p

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • DATA_RATE_CONFIG_p

    • Type: enum

      • Allowed values: ['SDR', 'DDR']

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

Worker Ports

    Interfaces (other than data I/O ports):

  • dev_cfg_data

    • Type: devsignal

  • dev_cfg_data_tx

    • Type: devsignal

  • dev_data_clk

    • Type: devsignal

  • dev_data_to_pins

    • Type: devsignal

  • dev_txen

    • Type: devsignal

  • dev_data_ch0_in

    • Type: devsignal

  • dev_data_ch1_in

    • Type: devsignal

  • dev_tx_event_ch0

    • Type: devsignal

  • dev_tx_event_ch1

    • Type: devsignal

    • Subdevice Connections:

    • Supported device worker: ad9361_dac


      Connections:


      • Subdevice port: dev_dac

      • Supported worker port: dev_data_ch1_in

        • Index: None


      • Subdevice port: dev_tx_event

      • Supported worker port: dev_tx_event_ch1

        • Index: None


Worker Signals

  • config_is_two_r

    • Direction: in

    • Differential: false

    • Pin: false

  • ch0_handler_is_present

    • Direction: out

    • Differential: false

    • Pin: false

  • ch1_handler_is_present

    • Direction: out

    • Differential: false

    • Pin: false

  • data_bus_index_direction

    • Direction: out

    • Differential: false

    • Pin: false

  • data_clk_is_inverted

    • Direction: out

    • Differential: false

    • Pin: false

  • islvds

    • Direction: out

    • Differential: false

    • Pin: false

  • isdualport

    • Direction: out

    • Differential: false

    • Pin: false

  • isfullduplex

    • Direction: out

    • Differential: false

    • Pin: false

  • isDDR

    • Direction: out

    • Differential: false

    • Pin: false

  • present

    • Direction: out

    • Differential: false

    • Pin: false

  • config_is_two_t

    • Direction: in

    • Differential: false

    • Pin: false

  • force_two_r_two_t_timing

    • Direction: in

    • Differential: false

    • Pin: false

  • DATA_CLK_P

    • Direction: in

    • Differential: false

    • Pin: false

  • data

    • Direction: out

    • Width: 24

    • Differential: false

    • Pin: false

  • tx_frame

    • Direction: out

    • Differential: false

    • Pin: false

  • txen

    • Direction: out

    • Differential: false

    • Pin: false

  • dac_clk

    • Direction: in

    • Differential: false

    • Pin: false

  • dac_ready

    • Direction: out

    • Differential: false

    • Pin: false

  • dac_take

    • Direction: in

    • Differential: false

    • Pin: false

  • dac_data_I

    • Direction: out

    • Width: 12

    • Differential: false

    • Pin: false

  • dac_data_Q

    • Direction: out

    • Width: 12

    • Differential: false

    • Pin: false

  • txon_pulse

    • Direction: out

    • Differential: false

    • Pin: false

  • txoff_pulse

    • Direction: out

    • Differential: false

    • Pin: false

  • event_in_connected

    • Direction: out

    • Differential: false

    • Pin: false

  • is_operating

    • Direction: out

    • Differential: false

    • Pin: false

Utilization

Utilization reporting is not currently implemented.

References