Appendix
Appendix - Vivado Timing Analysis
The Vivado timing report that OpenCPI runs for device workers may erroneously report a max delay for a clocking path which should have been ignored. Custom Vivado tcl commands had to be run for this device worker to extract pertinent information from Vivado timing analysis. After building the worker, the following commands were run from the assets project directory (after the Vivado settings64.sh was sourced):
cd hdl/devices/
vivado -mode tcl
Then the following commands were run inside the Vivado tcl terminal:
open_project ad9361_dac.hdl/target-zynq/ad9361_dac_rv.xpr
synth_design -part xc7z020clg484-1 -top ad9361_dac_rv -mode out_of_context
create_clock -name clk1 -period 0.001 [get_nets {ctl_in[Clk]}]
create_clock -name clk2 -period 0.001 [get_nets {dev_dac_in[dac_clk]}]
set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2]
The Fmax for the control plane clock for this worker is computed as the maximum magnitude slack with a control plane clock of 1 ps plus 2 times the assumed 1 ps control plane clock period (5.372 ns + 0.002 ns = 5.374 ns, 1/5.374 ns = 186.08 MHz). The Fmax for the dac_clk clock from the devsignal is computed as the maximum magnitude slack with dac_clk of 1 ps plus 2 times the assumed 1 ps dac_clk period (4.306 ns + 0.002 ns = 4.308 ns, 1/4.287 ns = 232.12 MHz).
The following command is run to get control plane clock timing:
report_timing -delay_type min_max -sort_by slack -input_pins -group clk1
The expected output of the command is as follows:
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port ``ctl_in[Clk]'' is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port ``dev_dac_in[dac_clk]'' is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type min_max -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.1 (lin64) Build 1846317 Fri Apr 14 18:54:47 MDT 2017
| Date : Wed Oct 3 16:41:06 2018
| Host : <removed> running 64-bit CentOS Linux release 7.5.1804 (Core)
| Command : report_timing -delay_type min_max -sort_by slack -input_pins -group clk1
| Design : ad9361_dac_rv
| Device : 7z020-clg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
-------------------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -5.372ns (required time - arrival time)
Source: IN_port/fifo/data0_reg_reg[13]/C
(rising edge-triggered cell FDRE clocked by clk1 {rise@0.000ns fall@0.001ns period=0.001ns})
Destination: worker/fifo/fifo/fifoMem_reg/DIADI[9]
(rising edge-triggered cell RAMB18E1 clocked by clk1 {rise@0.000ns fall@0.001ns period=0.001ns})
Path Group: clk1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 0.002ns (clk1 rise@0.002ns - clk1 rise@0.000ns)
Data Path Delay: 4.374ns (logic 1.904ns (43.533%) route 2.470ns (56.467%))
Logic Levels: 5 (CARRY4=3 LUT4=1 LUT5=1)
Clock Path Skew: -0.049ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.924ns = ( 0.926 - 0.002 )
Source Clock Delay (SCD): 0.973ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk1 rise edge) 0.000 0.000 r
0.000 0.000 r ctl_in[Clk] (IN)
net (fo=198, unset) 0.973 0.973 IN_port/fifo/ctl_in[Clk]
FDRE r IN_port/fifo/data0_reg_reg[13]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.518 1.491 r IN_port/fifo/data0_reg_reg[13]/Q
net (fo=3, unplaced) 0.759 2.250 IN_port/fifo/IN_data[5]
r IN_port/fifo/fifoMem_reg_i_36/I1
LUT4 (Prop_lut4_I1_O) 0.295 2.545 r IN_port/fifo/fifoMem_reg_i_36/O
net (fo=1, unplaced) 0.902 3.447 IN_port/fifo/fifoMem_reg_i_36_n_0
r IN_port/fifo/fifoMem_reg_i_24/I1
LUT5 (Prop_lut5_I1_O) 0.124 3.571 r IN_port/fifo/fifoMem_reg_i_24/O
net (fo=1, unplaced) 0.000 3.571 IN_port/fifo/fifoMem_reg_i_24_n_0
r IN_port/fifo/fifoMem_reg_i_5/S[0]
CARRY4 (Prop_carry4_S[0]_CO[3])
0.513 4.084 r IN_port/fifo/fifoMem_reg_i_5/CO[3]
net (fo=1, unplaced) 0.009 4.093 IN_port/fifo/fifoMem_reg_i_5_n_0
r IN_port/fifo/fifoMem_reg_i_4/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.210 r IN_port/fifo/fifoMem_reg_i_4/CO[3]
net (fo=1, unplaced) 0.000 4.210 IN_port/fifo/fifoMem_reg_i_4_n_0
r IN_port/fifo/fifoMem_reg_i_3/CI
CARRY4 (Prop_carry4_CI_O[1])
0.337 4.547 r IN_port/fifo/fifoMem_reg_i_3/O[1]
net (fo=1, unplaced) 0.800 5.347 worker/fifo/fifo/sD_IN[9]
RAMB18E1 r worker/fifo/fifo/fifoMem_reg/DIADI[9]
------------------------------------------------------------------- -------------------
(clock clk1 rise edge) 0.002 0.002 r
0.000 0.002 r ctl_in[Clk] (IN)
net (fo=198, unset) 0.924 0.926 worker/fifo/fifo/ctl_in[Clk]
RAMB18E1 r worker/fifo/fifo/fifoMem_reg/CLKBWRCLK
clock pessimism 0.000 0.926
clock uncertainty -0.035 0.891
RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_DIADI[9])
-0.916 -0.025 worker/fifo/fifo/fifoMem_reg
-------------------------------------------------------------------
required time -0.025
arrival time -5.347
-------------------------------------------------------------------
slack -5.372
report_timing: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2095.184 ; gain = 497.547 ; free physical = 7704 ; free virtual = 54670
The following command is run to get dev_dac.dac_clk timing:
report_timing -delay_type min_max -sort_by slack -input_pins -group clk2
The expected output of the command is as follows:
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type min_max -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.1 (lin64) Build 1846317 Fri Apr 14 18:54:47 MDT 2017
| Date : Thu Oct 4 10:56:37 2018
| Host : <removed> running 64-bit CentOS Linux release 7.5.1804 (Core)
| Command : report_timing -delay_type min_max -sort_by slack -input_pins -group clk2
| Design : ad9361_dac_rv
| Device : 7z020-clg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
-------------------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -4.306ns (required time - arrival time)
Source: worker/fifo/fifo/dEnqPtr_reg[0]/C
(rising edge-triggered cell FDCE clocked by clk2 {rise@0.000ns fall@0.001ns period=0.001ns})
Destination: worker/fifo/fifo/fifoMem_reg/ENARDEN
(rising edge-triggered cell RAMB18E1 clocked by clk2 {rise@0.000ns fall@0.001ns period=0.001ns})
Path Group: clk2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 0.002ns (clk2 rise@0.002ns - clk2 rise@0.000ns)
Data Path Delay: 3.781ns (logic 1.061ns (28.063%) route 2.720ns (71.937%))
Logic Levels: 3 (LUT2=1 LUT6=2)
Clock Path Skew: -0.049ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.924ns = ( 0.926 - 0.002 )
Source Clock Delay (SCD): 0.973ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk2 rise edge) 0.000 0.000 r
0.000 0.000 r dev_dac_in[dac_clk] (IN)
net (fo=35, unset) 0.973 0.973 worker/fifo/fifo/dev_dac_in[dac_clk]
FDCE r worker/fifo/fifo/dEnqPtr_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.518 1.491 r worker/fifo/fifo/dEnqPtr_reg[0]/Q
net (fo=1, unplaced) 0.965 2.456 worker/fifo/fifo/dEnqPtr[0]
r worker/fifo/fifo/dGDeqPtr_rep[0]_i_3/I0
LUT6 (Prop_lut6_I0_O) 0.295 2.751 r worker/fifo/fifo/dGDeqPtr_rep[0]_i_3/O
net (fo=1, unplaced) 0.449 3.200 worker/fifo/fifo/dGDeqPtr_rep[0]_i_3_n_0
r worker/fifo/fifo/dGDeqPtr_rep[0]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.124 3.324 r worker/fifo/fifo/dGDeqPtr_rep[0]_i_1/O
net (fo=18, unplaced) 0.506 3.830 worker/fifo/fifo/dGDeqPtr0
r worker/fifo/fifo/fifoMem_reg_i_1/I0
LUT2 (Prop_lut2_I0_O) 0.124 3.954 r worker/fifo/fifo/fifoMem_reg_i_1/O
net (fo=1, unplaced) 0.800 4.754 worker/fifo/fifo/fifoMem_reg_i_1_n_0
RAMB18E1 r worker/fifo/fifo/fifoMem_reg/ENARDEN
------------------------------------------------------------------- -------------------
(clock clk2 rise edge) 0.002 0.002 r
0.000 0.002 r dev_dac_in[dac_clk] (IN)
net (fo=35, unset) 0.924 0.926 worker/fifo/fifo/dev_dac_in[dac_clk]
RAMB18E1 r worker/fifo/fifo/fifoMem_reg/CLKARDCLK
clock pessimism 0.000 0.926
clock uncertainty -0.035 0.891
RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ENARDEN)
-0.443 0.448 worker/fifo/fifo/fifoMem_reg
-------------------------------------------------------------------
required time 0.448
arrival time -4.754
-------------------------------------------------------------------
slack -4.306