ad9361_adc HDL Worker

Detail

The ad9361_adc_sub.hdl subdevice worker supports the ad9361_adc.hdl device worker. The ad9361_adc_sub.hdl subdevice sends a data bus containing 24-bit parallel I/Q data in the AD9361’s DATA_CLK_P pin clock domain via the dev_adc dev signal port. Either of data streams from the two AD9361 RX channels may be sent to an instance of ad9361_adc.hdl. Which RX channel data stream is sent is determined within the ad9361_adc_sub.hdl subdevice worker. The Q0.15 I/Q values on the ad9361_adc.hdl output port are sign extended from the AD9361’s 12-bit I/Q ADC bus. For more information see Ad9361 adc sub (ad9361_adc_sub).

The ad9361_adc.hdl worker passes data from the dev_adc dev signal bus through an asynchronous First-In-First-Out (FIFO) buffer to achieve clock domain crossing. The FIFO’s output side is in the HDL container’s control clock domain. Note that the HDL container’s control clock rate is platform-specific. The FIFO’s depth in number of samples is determined at build-time by the fifo_depth parameter property. An overrun property indicates when samples have been dropped due to the FIFO being full, which is possible when backpressure overcomes the ADC sample rate for long enough to fill up the FIFO. The output data port generates messages whose length in bytes is determined at runtime by the messageSize property.

Control Timing and Signals

The ad9361_adc.hdl device worker contains two clock domains: the clock from the Control Plane, and the adc_clk clock from the dev signal.

The latency from the dev signal data bus to the output port is non-deterministic due to data flowing through an asynchronous FIFO with each side in a different clock domain. This non-determinism exists even in the absense of backpressure. In the presence of backpressure, the latency increases in an amount directly proportional to the degree to which the FIFO is full.

Performance and Resource Utilization

The FPGA resource utilization and Fmax are included for this worker. Fmax refers to the maximum allowable clock rate for any registered signal paths within a given clock domain for an FPGA design. Fmax in the table below is specific only to this worker and represents the maximum possible Fmax for any OpenCPI bitstream built with this worker included. Note that the Fmax value for a given clock domain for the final bitstream is often worse than the Fmax specific to this worker, even if this worker is the only one included in the bitstream. Note also that the DATA CLK P devsignal’s rate will only ever go as high as 245.76 MHz as shown in the reference manual.

Table 102: Resource Utilization Table for worker: ad9361_adc

Configuration

OCPI Target

Tool

Version

Device

Registers (Typ)

LUTs (Typ)

Fmax (MHz) (Typ) control plane clock

Fmax (MHz) (Typ) dev_adc.adc_clk clock

Memory/Special Functions

0

zynq

Vivado

2017.1

xc7z020clg484-1

188

133

202

339

RAMB18: 1

0

stratix4

Quartus

17.1.0

EP4SGX230KF40C2

187

185

N/A

N/A

N/A

0

virtex6

ISE

14.7

6vlx240tff1156-1

208

258

335.373

369

RAM64M: 8

Worker Properties

  • fifo_depth

    • Type: ulong

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • ocpi_buffer_size_OUT

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: True

      • Volatile: False

      • Read back: False

    • Default value: 0

  • ocpi_blocked_OUT

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_max_latency_OUT

    • Type: ushort

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • ocpi_latency_OUT

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_messages_OUT

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_bytes_OUT

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

Worker Ports

    Outputs:

  • OUT

    • Protocol: iqstream

    • Optional: True

    • Interfaces (other than data I/O ports):

  • dev_adc

    • Type: devsignal

Worker Signals

  • present

    • Direction: out

    • Differential: false

    • Pin: false

  • adc_data_I

    • Direction: in

    • Width: 12

    • Differential: false

    • Pin: false

  • adc_data_Q

    • Direction: in

    • Width: 12

    • Differential: false

    • Pin: false

  • adc_clk

    • Direction: in

    • Differential: false

    • Pin: false

  • adc_give

    • Direction: in

    • Differential: false

    • Pin: false

Utilization

Utilization reporting is not currently implemented.

References