cdc_fifo_tester HDL Worker
Detail
The cdc_fifo_tester worker uses a LFSR to generate data and the bits shifted out from LFSR are then used as the input to the fifo primitive. The data from the LFSR is enqueued as long as fifo is not full. The data is dequeued from the fifo primitive when the output port is ready for the data and the fifo is not empty.
The src_clk_hz and dst_clk_hz parameter properties are used to define the source and destination domain clock frequencies.
A clock generator is used to generate the clocks for the source and destination clock domains when the source and destination clock domains are different.
Worker Properties
ocpi_buffer_size_outType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
TrueVolatile:
FalseRead back:
False
Default value:
0
ocpi_blocked_outType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_max_latency_outType:
ushortAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
ocpi_latency_outType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_messages_outType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_bytes_outType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
Worker Ports
outProtocol:
NoneOptional:
False
Outputs:
Utilization
Utilization reporting is not currently implemented.