Cswm to iqstream (cswm_to_iqstream)

cswm_to_iqstream is an asset in the ocpi.assets.misc_comps component library. Implementations include cswm_to_iqstream HDL Worker (cswm_to_iqstream.hdl). Tested platforms include Rocky9, xsim.

Design

This component receives ComplexShortWithMetadata protocol messages from the in port and converts them to iqstream protocol messages that are transmitted to the out port. The messages for all possible ComplexShortWithMetadata opcodes are ingested, but only those with the samples opcode are converted and sent out the out port. This is due to the fact that ComplexShortWithMetadata has not only a data-related opcode, but multiple non-data-related opcodes, and the iqstream protocol only has a single, data-related opcode. All out port messages use the iqstream protocol’s iq opcode.

Block Diagram

= [rectangle, draw, fill=yellow!50, text width=20.5em, text centered, rounded corners, minimum height=4em] = [draw, -latex’] = [draw, ellipse,text width= 1em, fill=white!50, node distance=3cm, minimum height=1em]

Interface

<ComponentSpec>
  <Port name='in' producer='false' protocol='ComplexShortWithMetadata-prot'/>
  <Port name='out' producer='true' protocol='iqstream_protocol'/>
</ComponentSpec>

Properties

None.

Ports

Inputs:

  • in

    • Protocol: ComplexShortWithMetadata-prot

    • Optional: False

Outputs:

  • out

    • Protocol: iqstream_protocol

    • Optional: False

Implementations

Dependencies

The dependencies to other elements in OpenCPI are:

  • assets/hdl/primitives/misc_prims/prot_pkg.vhd

  • assets/hdl/primitives/misc_prims/misc_prims_pkg.vhd

  • assets/hdl/primitives/misc_prims/misc_prims_body.vhd

  • assets/hdl/primitives/misc_prims/counter.vhd

  • assets/hdl/primitives/misc_prims/prot/swi_message_sizer.vhd

  • assets/hdl/primitives/misc_prims/prot/cswm_demarshaller.vhd

  • assets/hdl/primitives/misc_prims/prot/iqstream_marshaller.vhd

  • assets/components/misc_comps/cswm_to_iqstream.hdl/cswm_to_iqstream.vhd

Limitations

Limitations of cswm_to_iqstream are:

  • None.

Testing

The Unit Under Test (UUT) is tested by a) generating a file containing protocol-formatted messages which are sent to the UUT via the file_read component, b) using the file_write component to save the file containing the UUT’s output as protocol-formatted message, and c) verifying the contents of the output file. The generated file contains one or more ComplexShortWithMetadata samples messages following followed by a message for each of the non-samples opcodes. The sequence of samples messages include samples whose I and Q signals are positive and negative ramp functions, respectively. The output file is verified by confirming that a) the same number of samples exists in the input and output files, and b) the output file contains the same ramp functions as the input.