Cdc bits tester (cdc_bits_tester)

cdc_bits_tester is an asset in the ocpi.assets.misc_comps component library. Implementations include cdc_bits_tester HDL Worker (cdc_bits_tester.hdl). Tested platforms include xsim, zed.

Design

The cdc_bits_tester serves as a testbench for the bits cdc primitive. The bits primitive synchronizes a bus of bits using single-bit multi-register synchronizers. The bits primitive’s width generic sets how many single-bit multi-register synchronizers to use. Coherency among the bus of bits is not guaranteed and is intended for uses cases where bits need to be synchronized but data coherency doesn’t matter. An example use case of the bits primitive is using it for status bits for unrelated conditions.

The worker generates data and sends the data through the bits synchronizer. The output of the synchronizer is sent to worker’s output port.

The cdc bits tester worker uses the clock from the Control Plane as input to the clock generator. The output of the clock generator is used to drive the output port clock.

A block diagram representation of the implementation is given in Figure 147:

Figure 147: cdc_bits_tester block diagram.

Interface

<ComponentSpec>


 <Property Name="src_clk_hz" Type="float"
                             Parameter="true"
                             Default="100000000.0"
                             Description="Source clock frequency"/>

  <Property Name="dst_clk_hz" Type="float"
                              Parameter="true"
                              Default="100000000.0"
                              Description="Destination clock frequency"/>

  <Property Name="num_input_samples" Type="uchar"
                                     Parameter="true"
                                     Default="15"
                                     Description="Number of input samples sent."/>

  <Port Name="out" Producer="true"/>

</ComponentSpec>

Properties

• src_clk_hz: Source clock frequency.

  • Type: float

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

  • Default value: 100000000.0

• dst_clk_hz: Destination clock frequency.

  • Type: float

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

  • Default value: 100000000.0

• num_input_samples: Number of input samples sent.

  • Type: uchar

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

  • Default value: 15

Ports

Inputs:

None.

Outputs:

• out

  • Protocol: None

  • Optional: False

Implementations

• cdc_bits_tester (HDL)

Dependencies

The dependencies to other elements in OpenCPI are:

• assets/components/misc_comps/cdc_bits_tester.hdl/cdc_bits_tester.vhd

• core/hdl/primitives/cdc/bits.vhd

• core/hdl/primitives/cdc/cdc_pkg.vhd

Limitations

Limitations of cdc_bits_tester are:

• None.

Testing

There are files used to validate the data the cdc_bits_tester worker sends. The files used in the verification were created from the output of the unit test when running the unit test in simulation and contain the expected output data when there is no metastability. Since there might or might not be a perfect match of the output data to the expected output data when running the tests in hardware due to metastability or phase offset, the output data is correlated with the expected output data. If there is at least a 0.7 positive Pearson product-moment correlation coefficient, then test case is considered passing. This correlation is only used when running the unit test on hardware. If the test are run in simulation, the output data is compared with expected output data. If they match exactly, then test case is considered passing.