cdc_bits_tester HDL Worker

Detail

The cdc_bits_tester worker instantiates the bits primitive with the input and output being 4 bits wide. The worker uses 4 LFSRs with each one having the same polynomial but different seeds. The bit shifted out from each LFSR is then used as the input to the bits primitive. Once the input signal has crossed into the destination clock domain it is stored in a FIFO until the worker’s output port is ready for the data. The FIFO is used because the data is sent only once and also used to mitigate synchronizing the backpressure from the output port to the LFSRs.

The src_clk_hz and dst_clk_hz parameter properties are used to define the source and destination domain clock frequencies.

A clock generator is used to generate the clocks for the source and destination clock domains when the source and destination clock domains are different.

Fast clock domain to slow clock domain:

When the source clock frequency is faster than destination clock frequency, the destination domain reset signal is sent through a reset synchronizer to synchronize it to the source domain. The source domain uses the synchronized reset to enable an advance_counter module that outputs a signal to enable the LFSRs. It is used to ensure that the minimum input signal width to the bits primitive is 2x the period of the destination clock and they are separated by 2x src_clk cycles to ensure proper crossing of the CDC boundary. See http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf - Section 4.4 and https://m.eet.com/media/1137372/17561-310388.pdf for more information on the 2x requirement. The FIFO is enabled when the destination clock domain has come out of reset.

Slow clock domain to fast clock domain:

When the source clock frequency is slower than the destination clock frequency, the LFSRs are enabled when the source domain has come out of reset. The source domain reset signal is sent through a reset synchronizer to synchronize it to the destination domain and is used to enable the FIFO.

Same clock domain:

When the source clock frequency is equal to the destination clock frequency, the destination domain reset signal is sent through a reset synchronizer to synchronize it to the source domain. The source domain uses the synchronized reset to enable an advance_counter. The source domain reset signal is sent through a reset synchronizer to synchronize it to the destination domain and is used to enable the FIFO.

Worker Properties

  • ocpi_buffer_size_out

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: True

      • Volatile: False

      • Read back: False

    • Default value: 0

  • ocpi_blocked_out

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_max_latency_out

    • Type: ushort

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • ocpi_latency_out

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_messages_out

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_bytes_out

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

Worker Ports

    Outputs:

  • out

    • Protocol: None

    • Optional: False

Utilization

Utilization reporting is not currently implemented.

References