platform_ad9361_spi HDL Subdevice Worker

HDL subdevice worker that provides an SPI state machine for communication with the AD9361 device.

Detail

The AD9361 SPI HDL subdevice worker implements a serial peripheral interface (SPI) state machine for communication with the AD9361 integrated circuit (IC). The AD9361 SPI HDL subdevice worker is intended for use in platforms and cards with an SPI bus that addresses only the AD9361. Properties are defined as <ComponentSpec> properties within the worker’s OpenCPI Worker Description (OWD); they are not defined in a separate OpenCPI Component Specification (OCS). SPI read/writes are actuated by the rprops RawProperty port. A DevSignal is also sent which can force the AD9361 RESETB pin, which is active-low, to logic 0.

A block diagram representation of the implementation is given in Figure 226:

AD9361 SPI HDL Subdevice Worker Implementation Block Diagram

Figure 226: AD9361 SPI HDL Subdevice Worker Block Diagram

Worker Properties

  • CP_CLK_FREQ_HZ_p

    • Type: float

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • SPI_CLK_FREQ_HZ_p

    • Type: float

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • lastAddr

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • lastData

    • Type: uchar

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • resetting

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

Worker Ports

    Interfaces (other than data I/O ports):

  • dev_force_reset: Forces the RESETB pin, which is active low, to logic 0.

    • Type: devsignal

  • rprops: Actuates SPI reads and writes to the AD9361 device.

    • Type: rawprop

    • Subdevice Connections:

    • Supported device worker: platform_ad9361_config


      Connections:


      • Subdevice port: rawprops

      • Supported worker port: rprops

        • Index: None


      • Subdevice port: dev_force_spi_reset

      • Supported worker port: dev_force_reset

        • Index: None


Worker Signals

  • force_reset

    • Direction: out

    • Differential: false

    • Pin: false

  • SPI_DI

    • Direction: out

    • Differential: false

    • Pin: false

  • SPI_CLK

    • Direction: out

    • Differential: false

    • Pin: false

  • SPI_ENB

    • Direction: out

    • Differential: false

    • Pin: false

  • SPI_DO

    • Direction: in

    • Differential: false

    • Pin: false

  • RESETB

    • Direction: out

    • Differential: false

    • Pin: false

Worker Configuration Parameters

  • Resource utilization for this worker for the zynq target platform, configuration 0:

    • Configuration: 0

    • Tool: Vivado

    • Version: 2017.1

    • Device: xc72020clg484-1

    • Registers (Typ): 67

    • LUTS (Typ): 94

    • Fmax (MHz) (Typ): 235

  • Resource utilization for this worker for the zynq target platform, configuration 1:

    • Configuration: 1

    • Tool: Vivado

    • Version: 2017.1

    • Device: xc72020clg484-1

    • Registers (Typ): 68

    • LUTS (Typ): 101

    • Fmax (MHz) (Typ): 315

  • Resource utilization for this worker for the stratix target platform, configuration 0:

    • Configuration: 1

    • Tool: Quartus

    • Version: 17.1.0

    • Device: EP4SGX230KF40C2

    • Registers (Typ): 70

    • LUTS (Typ): 139

    • Fmax (MHz) (Typ): N/A

  • Resource utilization for this worker for the stratix target platform, configuration 1:

    • Configuration: 1

    • Tool: Quartus

    • Version: 17.1.0

    • Device: EP4SGX230KF40C2

    • Registers (Typ): 71

    • LUTS (Typ): 141

    • Fmax (MHz) (Typ): N/A

  • Resource utilization for this worker for the virtex6 target platform, configuration 0:

    • Configuration: 0

    • Tool: ISE

    • Version: 14.7

    • Device: 6v1x240tff1 156-1

    • Registers (Typ): 65

    • LUTS (Typ): 130

    • Fmax (MHz) (Typ): 437.445

  • Resource utilization for this worker for the virtex6 target platform, configuration 1:

    • Configuration: 1

    • Tool: ISE

    • Version: 14.7

    • Device: 6v1x240tff1 156-1

    • Registers (Typ): 65

    • LUTS (Typ): 134

    • Fmax (MHz) (Typ): 412.712

Fmax refers to the maximum allowable clock rate for any registered signal paths within a given clock domain for an FPGA design. Fmax is specific only to this worker and represents the maximum possible Fmax for any OpenCPI bitstream built with this worker included. Note that the Fmax value for a given clock domain for the final bitstream is often worse than the Fmax specific to this worker, even if this worker is the only one included in the bitstream.

Note that the Fmax measurements given for the zynq target are the result of a Vivado timing analysis that is different from the Vivado analysis performed by default for OpenCPI worker builds. See the section “Vivado timing analysis” for details.

Control Timing and Signals

The AD9361 SPI HDL subdevice worker operates entirely in the control plane clock domain. All SPI data and SPI clock signals are generated in the control plane clock domain. Note that SPI clock can only be a divided version of the control plane clock.

Vivado Timing Analysis

The Vivado timing report that OpenCPI runs for HDL device workers may erroneously report a max delay for a clocking path which should have been ignored. Custom Vivado tcl commands had to be run for this HDL subdevice worker to extract pertinent information from Vivado timing analysis. After building the worker, the following commands were run from the assets project directory (after the Vivado settings64.sh was sourced):

cd hdl/devices/
vivado -mode tcl

Then the following commands were run inside the Vivado tcl terminal for the parameter property set:

  • CP_CLK_FREQ_HZ_p=100e6

  • SPI_CLK_FREQ_HZp=6.25e6

open_project ad9361_spi.hdl/target-zynq/ad9361_spi_rv.xpr
synth_design -part xc7z020clg484-1 -top ad9361_spi_rv -mode out_of_context
create_clock -name clk1 -period 0.001 [get_nets {ctl_in[Clk]}]
report_timing -delay_type min_max -sort_by slack -input_pins -group clk1

The Fmax for the control plane clock for this worker is computed as the maximum magnitude slack with a control plane clock of 1 ps plus 2 times the assumed 1 ps control plane clock period (4.244 ns + 0.002 ns = 4.244 ns, 1/4.244 ns = 235.52 MHz).

Then the following commands were run inside the Vivado tcl terminal for the parameter property set:

  • CP_CLK_FREQ_HZ_p=125e6

  • SPI_CLK_FREQ_HZp=6.25e6

open_project ad9361_spi.hdl/target-zynq/ad9361_spi_rv.xpr
synth_design -part xc7z020clg484-1 -top ad9361_spi_rv -mode out_of_context
create_clock -name clk1 -period 0.001 [get_nets {ctl_in[Clk]}]
report_timing -delay_type min_max -sort_by slack -input_pins -group clk1

The Fmax for the control plane clock for this worker is computed as the maximum magnitude slack with a control plane clock of 1 ps plus 2 times the assumed 1 ps control plane clock period (3.169 ns + 0.002 ns = 3.171 ns, 1/3.171 ns = 315.36 MHz).