data_src_qadc_csts HDL Device Worker

HDL device worker that provides functionality common to all ADC device types.

Detail

The data source Quadratic Analog-to-Digital Converter (QADC) Complex Short Timed Samples (CSTS) HDL device worker implements the data source Quadratic QADC CSTS component, which provides the property and port definitions necessary for the data source QADC CSTS HDL device worker to perform all the generic functionality required to ingest ADC data onto an FPGA.

Note

This HDL device worker is functionally equivalent to the data source QADC HDL device worker except that it specifies the Complex Short Timed Sample (CSTS) protocol in port definitions instead of the Complex Short With Metadata (CSWM) protocol. The CSTS version of this worker will replace the CSWM version in a future release.

A block diagram representation of the HDL device worker implementation is given in Figure 232:

Figure 232: Data Source QADC CSTS HDL Device Worker Block Diagram

The data source QADC CSTS HDL device worker receives sampled data from an ADC on its dev devsignal port. The worker sign-extends and justifies the samples to 16-bit real, 16-bit imaginary values, which is the standard provided by the samples argument of the complex_short_timed_sample-prot protocol used by the out port. The HDL device worker performs justification within the 16-bit values according to the value of the ADC_INPUT_IS_LSB_OF_OUT_PORT parameter property.

The ADC samples are sent along with the ADC clock on the dev devsignal port. The output port clock is driven by the ADC clock, and backpressure from the output port’s ready signal is not expected under normal operation. When backpressure is experienced, the overrun_sticky_error property is set to true; in this case, an out port samples message will be ended if one is in progress, and a sync message will be sent to the output port.

The samp_count_before_first_samp_drop component property gives the number of samples before the first dropped sample and the num_dropped_samps component property gives the number of samples dropped. Be sure to check these two properties at the end of an application run because they are not stable until then. The worker does not use clock domain crossing (cdc) HDL primitive library circuits for these properties because it takes advantage of the fact that they will have a stable value by the time the OpenCPI control plane reads them at the end of an application run.

When set to true, the suppress_discontinuity_opcode component property prevents the HDL device worker from sending sync opcodes.

When set to true, the send_eof worker property allows the HDL device worker to send an EOF after the number of samples specified in the num_samples_before_eof worker property have been sent.

For component properties implemented by this HDL device worker, see $OCPI_ROOT_DIR/projects/platform/hdl/devices/specs/data_src_qadc_csts-spec.xml.

Worker Properties

• send_eof

  • Type: bool

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: false

• num_samples_before_eof

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 4096

• DATA_PIPE_LATENCY_CYCLES

  • Type: ulong

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• OUT_PORT_DATA_WIDTH

  • Type: ulong

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_buffer_size_out

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_out

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_out

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Outputs:

• out: Sign-extended justified 16-bit complex samples.

  • Protocol: complex_short_timed_sample

  • Optional: False

Interfaces (other than data I/O ports):

• dev

  • Type: devsignal

Worker Signals

• clk

  • Direction: in

  • Differential: false

  • Pin: false

• data_i

  • Direction: in

  • Width: 16

  • Differential: false

  • Pin: false

• data_q

  • Direction: in

  • Width: 16

  • Differential: false

  • Pin: false

• valid

  • Direction: in

  • Differential: false

  • Pin: false

• present

  • Direction: out

  • Differential: false

  • Pin: false