data_sink_qdac_csts HDL Device Worker

HDL device worker that provides functionality common to all DAC device types.

Detail

The data sink Quadratic Digital-to-Analog-Converter (QDAC) Complex Short Timed Sample (CSTS) HDL device worker implements the data sink QDAC CSTS component specification, which provides the properties and ports that are necessary for this HDL device worker to implement the functionality that is common to all Digital-to-Analog Converter (DAC) device types. This functionality includes:

• Interpreting input messages indicating end of data and finishing on end-of-file (EOF)

• Normalizing input data to the bit width of the device

• Providing an underrun indicator when the rate of input data is less than the DAC data rate

The data sink QDAC CSTS HDL device worker is intended to be paired with an HDL subdevice worker that translates the dev interface to a device-specific interface.

Note

This HDL device worker is functionally equivalent to the data sink QDAC HDL device worker except that it specifies the Complex Short Timed Sample (CSTS) protocol in port definitions instead of the Complex Short With Metadata (CSWM) protocol. The CSTS version of this worker will replace the CSWM version in a future release.

A block diagram representation of the HDL device worker implementation is given in Figure 230:

Figure 230: Data Sink QDAC CSTS HDL Device Worker Block Diagram

Note

In the figure above, “WSI” refers to the Worker Streaming Interface, which is described in the OpenCPI HDL Development Guide.

Be sure to check the samp_count_before_first_underrun and num_underruns component properties at the end of an application run because they are not stable until that time. The worker does not use clock domain crossing (cdc) HDL primitive library circuits for these properties because it takes advantage of the fact that they will have a stable value by the time the OpenCPI control plane reads them at the end of an application run.

For component properties implemented by this HDL device worker, see $OCPI_ROOT_DIR/projects/platform/hdl/devices/specs/data_sink_qadc_csts-spec.xml.

Worker Properties

• IN_PORT_DATA_WIDTH

  • Type: ulong

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• unused_opcode_detected_sticky

  • Type: bool

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• clr_unused_opcode_detected_sticky

  • Type: bool

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• dac_clk_freq_hz

  • Type: float

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• status

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ctl_count

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• dac_count

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_buffer_size_on_off

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_on_off

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_on_off

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_on_off

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_on_off

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_on_off

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• in: Size defined by IN_PORT_DATA_WIDTH.

  • Protocol: complex_short_timed_sample

  • Optional: False

Outputs:

• on_off: See the section “Streaming Data Interfaces to/from an HDL Worker” in the OpenCPI HDL Development Guide for instructions on calculating the default value.

  • Protocol: tx_event

  • Optional: True

Interfaces (other than data I/O ports):

• dev

  • Type: devsignal

Worker Signals

• clk

  • Direction: in

  • Differential: false

  • Pin: false

• data_i

  • Direction: out

  • Width: 16

  • Differential: false

  • Pin: false

• data_q

  • Direction: out

  • Width: 16

  • Differential: false

  • Pin: false

• valid

  • Direction: out

  • Differential: false

  • Pin: false

• present

  • Direction: out

  • Differential: false

  • Pin: false