iq_imbalance_fixer_xs HDL Worker

An HDL implementation of the IQ Imbalance Fixer

Detail

The IQ Imbalance Fixer worker inputs complex signed samples and removes the spectral image caused by a quadrature gain imbalance between I and Q rails and also by a phase imbalance (not a perfect 90 degrees between sine and cosine) between the complex rails. The averaging time and the error loop gain of the worker are programmable, as is the ability to bypass the worker and to update/hold the calculated error correction values.

Samples are stored in the forward path of the primitive, and are pushed through the pipeline to the output on reception of more samples or an EOF. The following routine is required upon reception of non-sample opcodes to ensure that they have no discernible impact on the order of the output messages or on the algorithm i.e. the same feedback is calculated and applied at the same point in the received samples whether or not they are split over multiple messages:

• Do not immediately take the incoming non-sample opcode.

• Freeze the algorithm.

• Output the samples stored in the forward path whilst applying the normal forward path processing (overflow detection, etc).

• Take and output the incoming opcode and any further non-sample opcodes.

• Return the algorithm, including the forward path, to its pre-frozen state.

• Mark the forward path samples as valid for use in the feedback but as invalid for output, preventing repeating the samples that have already been sent.

An enable property is available to either enable (true) or bypass (false) the circuit. Note that bypass registers are not used. Instead, feedback error values are held constant at values that do not alter the Q rail. The update property, by default true, may be disabled to hold the loop errors to a constant value. Note that the enable property takes priority over the update property.

This worker can handle a new input sample every clock cycle with the output becoming available after fifteen valid input samples.

A flush and a discontinuity opcode are handled identically. Zero-valued samples are inserted into the pipeline to clock the samples still held in the corrector out to the output, where they complete the preceding message; the inserted samples are themselves discarded (not output). The forward pipeline and loop error accumulators are then cleared before the opcode is forwarded. The calculated power and phase corrections are retained, so correction resumes from its current state rather than restarting from unity gain.

Worker Properties

• log2_averaging_length_max

  • Type: uchar

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_buffer_size_output

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_output

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_output

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• input

  • Protocol: complex_short_timed_sample

  • Optional: False

Outputs:

• output

  • Protocol: complex_short_timed_sample

  • Optional: False

Limitations

The limitations of the iq_imbalance_fixer_xs HDL worker are:

• The protocol interface FIFO has a fixed depth of 8, so too many (more than 8) short messages input back to back may cause an overflow.

• The processing pipeline only advances on valid sample data, so the final samples of a message (up to the pipeline depth) remain internal until further sample data, a flush or discontinuity opcode, or an end-of-file arrives. Non-sample opcodes (time, sample interval and metadata) do not advance the pipeline and are queued, in order, behind any sample data still held within it.

Utilisation

Utilization reporting is not currently implemented.