crc_generator_b HDL Worker

Galois linear feedback shift register (LFSR) HDL implementation.

Detail

In a Galois LFSR implementation each XOR gate requires only two inputs and is positioned between consecutive registers. In the alternative Fibonacci LFSR implementation the XOR gates are cascaded which results in greater propagation delay between registers and therefore negatively affects timing performance. However modern FPGA’s can take advantage of their LUT architecture and implement the cascaded XOR gates as a single multi-port XOR gate.

For detail on the implementation of the HDL worker refer to the CRC serial primitive for further detail.

The size of the polynomial sets the number of shift registers required to implement the LFSR.

Worker Properties

  • ocpi_buffer_size_output

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: True

      • Volatile: False

      • Read back: False

    • Default value: 0

  • ocpi_blocked_output

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_max_latency_output

    • Type: ushort

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • ocpi_latency_output

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_messages_output

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ocpi_bytes_output

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

Worker Ports

    Inputs:

  • input

    • Protocol: bool_timed_sample

    • Optional: False

    • Outputs:

  • output

    • Protocol: bool_timed_sample

    • Optional: False

Utilisation

Utilization reporting is not currently implemented.