HDLC Framer (`hdlc_framer_uc_b`)

Generates an HDLC frame by inserting opening/closing flags, appending a CRC, and performing bit stuffing.

Design

On receiving data, an HDLC frame is generated when either:

A discontinuity message is received

A flush message is received

An EOF event occurs

The max_payload_size input samples limit has been received

Input data has to have been received previously for a frame to be generated. The component processes incoming payload bytes by appending a CRC, inserting start/end flags (0x7E), and applying bit stuffing (to the payload and CRC). This results in an output format (left-to-right) of [ 0x7E ] [ Payload ] [ CRC ] [ 0x7E ]. Bit stuffing is used to ensure that six consecutive ones never occur within the payload or CRC, preventing them from being misidentified as the flags.

Interface

<?xml version="1.0"?>
<componentspec>
  <property name="polynomial_taps" type="uchar" arraylength="32" parameter="true" default="16,12,5"
    description="CRC polynomial taps."/>
  <property name="max_payload_size" type="ushort" parameter="true" default="32"
    description="Maximum number of payload bytes per frame."/>
  <property name="input_reflect" type="bool" parameter="true" default="false"
    description="False is input data most significant bit first and true is least significant bit first."/>
  <property name="output_reflect" type="bool" parameter="true" default="false"
    description="False is CRC most significant bit first and true is least significant bit first."/>
  <property name="seed" type="ulong" writable="true" default="0" description="Initial seed for the CRC."/>
  <property name="final_xor" type="ulong" writable="true" default="0" description="Value to XOR the CRC result with."/>
  <port name="input" producer="false" protocol="uchar_timed_sample-prot"/>
  <port name="output" producer="true" protocol="bool_timed_sample-prot"/>
</componentspec>

Ports

Inputs:

input: Primary input samples port.
- Protocol: uchar_timed_sample-prot
- Optional: False

Outputs:

output: Primary output samples port.
- Protocol: bool_timed_sample-prot
- Optional: False

Opcode Handling

Received samples less than max_payload_size result in the first part of a frame being output immediately (without a CRC and end flag).

When a flush, discontinuity or EOF are received, a CRC is generated, it is bit-stuffed, and output with an end flag appended to it. The flush, discontinuity or EOF follow afterwards.

All other opcode messages pass through this component without any effect.

Properties

polynomial_taps: CRC polynomial taps. An array of up to 32 unsigned characters, meaning a maximum of 32 taps can be specified. If the polynomial is \(x^16+x^12+x^5+1\) then polynomial_taps should be set to “16,12,5”. There is no need to specify the \(x^0\) term, this is implied.
- Type: uchar
  - Array dimensions: ['32']
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 16,12,5
max_payload_size: Maximum number of payload bytes per frame.
- Type: ushort
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: 32
input_reflect: False is input data most significant bit first and true is least significant bit first.
- Type: bool
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: false
output_reflect: False is CRC most significant bit first and true is least significant bit first.
- Type: bool
- Access:
  - Parameter: True
  - Writable: False
  - Initial: False
  - Volatile: False
- Default value: false
seed: Initial seed for the CRC.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: 0
final_xor: Value to XOR the CRC result with.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: 0

Implementations

hdlc_framer_uc_b (HDL)
hdlc_framer_uc_b (RCC)

Example Application

<?xml version="1.0"?>
<application done="file_write">
  <instance component="ocpi.core.file_read" connect="hdlc_framer_uc_b">
    <property name="filename" value="input.bin"/>
  </instance>
  <instance component="ocpi.comp.sdr.communication.hdlc_framer_uc_b" connect="file_write">
    <property name="polynomial_taps" value="16,12,5"/>
    <property name="max_payload_size" value="32"/>
    <property name="input_reflect" value="true"/>
    <property name="output_reflect" value="false"/>
    <property name="seed" value="0xffff"/>
    <property name="final_xor" value="0xffff"/>
  </instance>
  <instance component="ocpi.core.file_write">
    <property name="filename" value="output.bin"/>
  </instance>
</application>

Dependencies

The dependencies to other elements in OpenCPI are:

CRC serial primitive

Bit stuffer primitive

There is also a dependency on:

ieee.std_logic_1164

ieee.numeric_std

ieee.math_real

Limitations

Limitations of hdlc_framer_uc_b are:

CRC sizes above 32 are not supported.

Sample interval opcodes pass through unmodified.

Testing

Tested platforms: None

Component testing not completed.

HDLC Framer (hdlc_framer_uc_b)