Timestamper scdcd (timestamper_scdcd)

timestamper_scdcd is an asset in the ocpi.assets.util_comps component library. Implementations include timestamper_scdcd HDL Worker (timestamper_scdcd.hdl). Tested platforms include xsim (Vivado 2017.1) zed.

Design

The timestamper_scdcd component contains the properties and ports for facilitating timestamping of complex samples with separate control and data clock domains (hence the name “scdcd”). Note that the actual separation of the clock domain is enforced by the HDL OWD, and not the OCS.

A block diagram representation of the implementation is given in Figure 171:

timestamper_scdcd block diagram.

Figure 171: timestamper_scdcd block diagram.

Interface

<ComponentSpec>

  <Property name='bypass'
            type='bool'
            writable='true'
            default='false'
            description='Forces in port messages to be sent directly to out
            port, bypassing the timestamping functionality.'/>
  <Property name='time_correction'
            type='longlong'
            writable='true'
            default='0'
            description='Q32.32 time correction value which is subtracted from
            the applied time (note Qm.n implies existence of a sign bit).'/>
  <Property name='correction_overflow_sticky'
            type='bool'
            volatile='true'
            description='Sticky bit overflow indication of correction
            calculation.'/>
  <Property name='clr_correction_overflow_sticky'
            type='bool'
            writable='true'
            default='false'
            description='Writing a value of true clears
            correction_overflow_sticky.'/>
  <Property name='force_error_on_invalid_time_at_start'
            type='bool'
            initial='true'
            default='false'
            description='Forces worker into the unusable state if the time
            invalid signal is low during the worker initialized state.'/>
  <Property name='samples_per_timestamp'
            description='After each timestamp, this number of samples is passed before the next one.
                         If zero, a timestamp precedes each sample output message (not recommended).'
            type='ulong'
            writable='true'
            default='1m'/>
  <Property name='sampling_interval' type='ulonglong' writable='true' default='0'
	    description='The fraction of a second between samples, in Q0.64 fixed point format.
                         Send in the stream if non-zero, upon start or when written'/>
  <Port name='in' producer='false' protocol='ComplexShortWithMetadata-prot'/>
  <Port name='out' producer='true' protocol='ComplexShortWithMetadata-prot'/>

</ComponentSpec>

Properties

  • bypass: Forces in port messages to be sent directly to out port, bypassing the timestamping functionality.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: false

  • time_correction: Q32.32 time correction value which is subtracted from the applied time (note Qm.n implies existence of a sign bit).

    • Type: longlong

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: 0

  • correction_overflow_sticky: Sticky bit overflow indication of correction calculation.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

    • Default value: None

  • clr_correction_overflow_sticky: Writing a value of true clears correction_overflow_sticky.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: false

  • force_error_on_invalid_time_at_start: Forces worker into the unusable state if the time invalid signal is low during the worker initialized state.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: True

      • Volatile: False

    • Default value: false

  • samples_per_timestamp: After each timestamp, this number of samples is passed before the next one. If zero, a timestamp precedes each sample output message (not recommended).

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: 1m

  • sampling_interval: The fraction of a second between samples, in Q0.64 fixed point format. Send in the stream if non-zero, upon start or when written.

    • Type: ulonglong

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: 0

Ports

Inputs:

  • in

    • Protocol: ComplexShortWithMetadata-prot

    • Optional: False

Outputs:

  • out

    • Protocol: ComplexShortWithMetadata-prot

    • Optional: False

Implementations

Dependencies

The dependencies to other elements in OpenCPI are:

  • projects/assets/components/util_comps/timestamper_scdcd.hdl/timestamper_scdcd.vhd

  • projects/assets/components/util_comps/timestamper_scdcd.hdl/cdc_fifo_complex_short_with_metadata.vhd

  • projects/assets/hdl/primitives/misc_prims/misc_prims_pkg.vhd

  • projects/assets/hdl/primitives/misc_prims/misc_prims_body.vhd

  • projects/assets/hdl/primitives/misc_prims/level_to_pulse_converter.vhd

  • projects/core/hdl/primitives/cdc/cdc_pkg.vhd

  • projects/core/hdl/primitives/cdc/fifo.vhd

  • projects/core/hdl/primitives/cdc/fast_pulse_to_slow_sticky.vhd

  • projects/core/hdl/primitives/cdc/single_bit.vhd

  • projects/assets/components/misc_comps/cswm_to_iqstream.hdl/cswm_to_iqstream.vhd

  • projects/assets/components/misc_comps/iqstream_to_cswm.hdl/iqstream_to_cswm.vhd

  • projects/core/hdl/primitives/util/util_pkg.vhd

  • projects/core/hdl/primitives/util/util_body.vhd

  • projects/core/hdl/primitives/ocpi/zlm_detector.vhd

  • projects/assets/hdl/primitives/misc_prims/time_downsampler.vhd

  • projects/assets/hdl/primitives/misc_prims/advance_counter.vhd

  • projects/assets/hdl/primitives/misc_prims/cdc_pkg.vhd

  • projects/assets/hdl/primitives/misc_prims/cdc_fifo_info.vhd

  • projects/core/hdl/primitives/util/set_clr.vhd

  • projects/core/hdl/primitives/protocol/message_sizer.vhd

Limitations

Limitations of timestamper_scdcd are:

  • None.

Testing

The test for the timestamper_scdcd uses a ramp of 512 samples that is generated by the generate.py script. Multiple files are created with varying parameters. The first parameter,time correction, which can be -1,0, or 1. The second, minimum number of samples for each timestamp, can be 0,1,1024,4091,4092, or 4093. The last variable is forcing an error if there is an invalid time, which can be set to true or false.

For verification, the output file is checked to see if SAMPLES, SYNC and TIME messages were received. All possible opcodes are sent through the UUT, and then it is verified that the previously mentioned ones were received and pass. The test fails if there are 0 TIME/SAMPLES received and if any number other than 1 SYNC message is received. The output file is also compared to a positive ramp function for I values, and a negative ramp function for Q values.