Protocol Interface Delay (protocol_interface_delay)

Delays OpenCPI interface signals to align them with a processed data signal.

Design

When data processing is performed on a stream of input data it typically results in a valid output one or more clock cycles after the input. This primitive delays OpenCPI interface signals in order to align them with a processed data stream. When the input opcode is equal to PROCESSED_DATA_OPCODE_G the processed data stream is output instead of the delayed input data.

Implementation

A shift register of length DELAY_G is constructed for each of the interface signals (SOM (start of message), EOM (end of message), valid, byte_enable, opcode, and data). A shift register of length DELAY_G is also constructed for the interface take signal to keep track of when data was actually taken from the input interface.

The DELAY_G value is set to the same length as the delay present between the input signal and the processed data. As such, at the end of the shift registers, the interface signals are correctly aligned with the processed data. A multiplexer is used to select either the processed data signal or the delayed input signal. Processed data is selected when the delayed opcode signal is equal to PROCESSED_DATA_OPCODE_G and the delayed valid signal is 1. The output give signal is driven whenever the delayed version of the interface take signal is 1 and the output interface is ready to accept data.

If the output interface is not ready to accept data then the delay shift registers are not advanced. This means for every input signal an output signal is generated after a delay of DELAY_G clock cycles where the output is ready to accept data.

Interface

Generics

  • DELAY_G (integer): Sets the length of the interface delay (in clock cycles) to be added.

  • DATA_WIDTH_G (integer): Sets the width of the interface data signal.

  • OPCODE_WIDTH_G (integer): Sets the width of the interface opcode signal.

  • BYTE_ENABLE_WIDTH_G (integer): Sets the width of the interface byte enable signal.

  • PROCESSED_DATA_MUX_G (std_logic): When 1 and the delayed interface opcode signal is equal to PROCESSED_DATA_OPCODE_G, then data from the processed_stream_in signal should be used for the output data signal instead of the delayed input data signal. When 0 the delayed data signal is always used.

  • PROCESSED_DATA_OPCODE_G (std_logic_vector): Sets the value of the opcode for which the processed_stream_in signal should be used for the output data signal instead of the delayed input data signal.

Ports

  • clk (std_logic), in: Clock. Inputs and outputs registered on rising edge.

  • reset (std_logic), in: Reset. Active high, synchronous with rising edge of clock.

  • enable (std_logic), in: Enable. Primitive enabled when high.

  • take_in (std_logic), in: High when data is taken from the input interface.

  • processed_stream_in (std_logic_vector, DATA_WIDTH_G bits), in: The processed data stream. I.e. the data this primitive is aligning the interface signals with.

  • input_som (std_logic), in: SOM signal from OpenCPI interface.

  • input_eom (std_logic), in: EOM signal from OpenCPI interface.

  • input_valid (std_logic), in: Valid signal from OpenCPI interface.

  • input_byte_enable (std_logic_vector, BYTE_ENABLE_WIDTH_G bits), in: Byte enable signal from OpenCPI interface.

  • input_opcode (std_logic_vector, OPCODE_WIDTH_G bits), in: Opcode signal from OpenCPI interface.

  • input_data (std_logic_vector, DATA_WIDTH_G bits), in: Data signal from OpenCPI interface.

  • output_som (std_logic), out: SOM signal on output OpenCPI interface.

  • output_eom (std_logic), out: EOM signal on output OpenCPI interface.

  • output_valid (std_logic), out: Valid signal on output OpenCPI interface.

  • output_give (std_logic), out: Give signal on output OpenCPI interface.

  • output_byte_enable (std_logic_vector, BYTE_ENABLE_WIDTH_G bits), out: Byte enable signal on output OpenCPI interface.

  • output_opcode (std_logic_vector, OPCODE_WIDTH_G bits), out: Opcode signal on output OpenCPI interface.

  • output_data (std_logic_vector, DATA_WIDTH_G bits), out: Data signal on output OpenCPI interface.

Dependencies

The dependencies to other elements in OpenCPI are:

  • None.

There is also a dependency on:

  • ieee.std_logic_1164

  • ieee.numeric_std

Limitations

Limitations of protocol_interface_delay are:

  • DELAY_G must be greater than zero.