complex_mixer.hdl HDL Worker

Detail

The HDL worker leverages Xilinx Vivado IP cores to implment the NCO (DDS Compiler) and complex multiply (Complex Multiplier) function. The make files in this worker generated the cores dependent on the version of Vivado installed and part you are building for.

Worker Properties

• data_select

  • Type: bool

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: false

• ocpi_buffer_size_out

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_out

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_out

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• in

  • Protocol: iqstream

  • Optional: False

Outputs:

• out

  • Protocol: iqstream

  • Optional: False

Utilization

Utilization reporting is not currently implemented.