E31x Platform Worker

Functionality

The E31x Platform worker is the interface between the Processing System and the FPGA on the Ettus E310 Platform. It makes the connections between the AXI buses on the ARM and the OpenCPI Control and Data Planes.

Worker Implementation Details

The E31X Platform Worker provides the device, device proxy, and application workers with interfaces to the control and data planes as necessary. The Platform Worker also instantiates and connects to the time_server.hdl device worker. A block diagram of the full Board Support Package, including device workers, device proxy workers, the platform Worker, and their connections is shown below:

Daughterboard

This platform contains a daughterboard which is comprised of an AD9361 RF IC, an analog filter bank along with control signals, and an AD5662 IC. Each of these has one or more device workers and/or a device proxy worker for control. Because the AD9361 device workers are platform-agnostic, they do not contain E310-specific support. More information on each of these workers can be found in its respective data sheet.

Block Diagrams

Top level

State Machines

Various state machines exist in the zynq, axi, and sdp primitive libraries. See primitive library source code for details. The explicit source code files included in the aforementioned primitives are enumerated in the following section.

Component Ports

No ports are implemented for the given component specification.

Worker Properties

• sdp_channels

  • Type: ulong

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• use_acp

  • Type: bool

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• useGP1

  • Type: bool

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• pps_src

  • Type: uchar

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• axi_error

  • Type: bool

    • Array dimensions: ['4']

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• sdpDropCount

  • Type: uchar

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• debug_state

  • Type: ulonglong

    • Array dimensions: ['4']

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• debug_state1

  • Type: ulonglong

    • Array dimensions: ['4']

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• debug_state2

  • Type: ulonglong

    • Array dimensions: ['4']

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• onswitch_db_p

  • Type: bool

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Signals

• PPS_EXT_IN

  • Direction: in

  • Differential: false

  • Pin: false

• GPS_PPS

  • Direction: in

  • Differential: false

  • Pin: false

• PL_GPIO

  • Direction: out

  • Width: 6

  • Differential: false

  • Pin: false

• ONSWITCH_DB

  • Direction: in

  • Differential: false

  • Pin: false

Worker Devices on E31X MIMO XCVR Card

The following is a table which enumerates which device workers are allowed in platform configurations and in assembly containers. The parameter values specify restricted/allowed implementations. Note that the worker signals listed are only those who are unconnected on the platform or whose platform signal name differ from the worker signal name. Note that device workers allowed by cards are not included in this list.

• e31x mimo xcvr ad5662

• e31x i2c

• e31x mimo xcvr filter

• ad9361 spi

  • Property Name: CP CLK FREQ HZ p

    • Property Value: 100e6

• ad9361 data sub

  • Property Name: lvds p

    • Property Value: false

  • Property Name: half duplex p

    • Property Value: false

  • Property Name: single port p

    • Property Value: true

  • Property Name: swap ports p

    • Property Value: false (true also supported)

  • Property Name: DATA CLK Delay

    • Property Value: 7

  • Property Name: RX Data Delay

    • Property Value: 0

  • Property Name: FB CLK Delay

    • Property Value: 12

  • Property Name: TX Data Delay

    • Property Value: 0

• ad9361 adc sub

  • Property Name: lvds p

    • Property Value: false

  • Property Name: half duplex p

    • Property Value: false

  • Property Name: single port p

    • Property Value: true

• ad9361 dac sub

  • Property Name: lvds p

    • Property Value: false

  • Property Name: half duplex p

    • Property Value: false

  • Property Name: single port p

    • Property Value: true

• ad9361 adc0

• ad9361 dac0

• ad9361 adc1

• ad9361 dac1

Control Timing and Signals

Control Domain

All control clocking in the E31X platform originates from the PS7 processing clock 1 (FCLK1), which is set to 100 MHz.

Sampling Domain

The sampling clock domain originates from the AD9361’s DATA_CLK_P output. It is labeled CAT_DATA_CLK on the daughterboard connector, and is ultimately assigned to the E31X_CONN_CAT_DATA_CLK input pin in the constraints file. This clock is routed to the AD9361 device workers (specifically ad9361_data_sub.hdl) via OpenCPI card/slot constructs.

This clock is used by the ad9361_adc_sub.hdl and ad9361_dac_sub.hdl workers. Additionally, the ad9361_dac_sub.hdl generates FB_CLK, which is routed through the card/slot to the E31X_CONN_CAT_FB_CLK output pin in the constraints file. This clock is transmitted alongside TX data in a source synchronous fashion. See the AD9361 device worker documentation and ADI’s UG-570 for more information regarding the relationships between these clocks.

Performance and Resource Utilization

Note that there are many possible configurations of this platform. For each combination of CMOS Single/Dual Port, Half/Full Duplex and ports-swapped/not swapped, there is also a 0rx1tx, 1rx0tx, 1rx1tx, … 2rx2tx. The resource utilization is only listed here for some of these, but can be extracted from the synthesized platform configuration for the supported modes. For now, the only supported modes are those corresponding to CMOS Single Port Full Duplex.

Test and Verification

Testing performed to verify functionality of the Platform Worker includes running of basic unit/application tests to test the Platform Worker itself, as well as device worker unit tests and system level application tests.

To test the basic functionality of the Platform Worker, simple applications such as testbias and unit tests such as bias.test were executed. These verify the basic functionality of the Platform Worker and its communication with the xilinx13_4 Software Platform.

To further test the Platform Worker’s functionality paired with its device workers, device worker unit tests were modified and performed for the AD9361 device workers, the E31X XCVR Filter device worker and proxy, the AD5662 device worker, and the RX and TX proxy workers. Each of these tests has its own document that can be reviewed for further information.

Finally, OpenCPI reference applications were modified and tested on the E310 radio using the AD9361 workers in CMOS Single Port Full Duplex DDR mode. This provides a full system test along the RX and TX paths.