Gain (gain)

Multiplies all input sample values by a fixed gain value.

Design

The mathematical representation of the implementation is given in (124).

(124)\[y[n] = G * x[n]\]

In (124):

• \(x[n]\) is the input values.

• \(y[n]\) is the output values.

• \(G\) is the gain factor.

If the gain is negative the output signal will be inverted with respect to the input signal.

A block diagram representation of the implementation is given in Figure 403:.

Figure 403: Gain implementation.

There is no rounding in this implementation, the output is allowed to overflow.

Interface

<?xml version="1.0"?>
<componentspec>
  <property name="gain" type="short" writable="true" default="4" description="Gain multiplier value."/>
  <property name="input_port_width" type="uchar" parameter="true" default="16" description="Sets the input bus width"/>
  <property name="output_port_width" type="uchar" parameter="true" default="32" description="Sets the output bus width"/>
  <property name="signed_data" type="bool" parameter="true" default="true"
    description="Controls whether the input and output are signed"/>
  <property name="complex_data" type="bool" parameter="true" default="false"
    description="Controls whether the input and output are complex"/>
  <property name="overflow" type="bool" writable="true" volatile="true"
    description="Indicates when an overflow occurred, write to reset"/>
  <port name="input" producer="false" numberofopcodes="6" defaultbuffersize="16384"/>
  <port name="output" producer="true" numberofopcodes="6" defaultbuffersize="16384"/>
</componentspec>

Opcode Handling

Only values in sample opcode messages are multiplied by a gain value.

All other opcode messages received are passed through this component without any effect.

Properties

• gain: Gain multiplier value.

  • Type: short

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: False

  • Default value: 4

• input_port_width: Sets the input bus width.

  • Type: uchar

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

  • Default value: 16

• output_port_width: Sets the output bus width.

  • Type: uchar

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

  • Default value: 32

• signed_data: Controls whether the input and output are signed.

  • Type: bool

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

  • Default value: true

• complex_data: Controls whether the input and output are complex.

  • Type: bool

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

  • Default value: false

• overflow: Indicates when an overflow occurred, write to reset.

  • Type: bool

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

  • Default value: None

Ports

Inputs:

• input: Primary input samples port.

  • Protocol: None

  • Optional: False

Outputs:

• output: Primary output samples port.

  • Protocol: None

  • Optional: False

Implementations

• gain (HDL)

• gain (RCC)

Example Application

<?xml version="1.0"?>
<application done="file_write">
  <instance component="ocpi.core.file_read" connect="gain">
    <property name="filename" value="input.bin"/>
  </instance>
  <instance component="ocpi.comp.sdr.math.gain" connect="file_write">
    <property name="gain" value="4"/>
    <property name="input_port_width" value="16"/>
    <property name="output_port_width" value="32"/>
    <property name="signed_data" value="true"/>
    <property name="complex_data" value="true"/>
  </instance>
  <instance component="ocpi.core.file_write">
    <property name="filename" value="output.bin"/>
  </instance>
</application>

Dependencies

The dependencies to other elements in OpenCPI are:

• HDL OpenCPI dependencies:

  • Opcode to SLV function

  • Opcode enumeration type

  • Protocol interface delay (narrow to wide) primitive v2

• RCC OpenCPI dependencies:

  • components/util/common/opcodes.hh

There are dependencies on the following VHDL libraries:

• ieee.std_logic_1164

• ieee.numeric_std

Limitations

Limitations of gain are:

• Applying a negative gain when the signed property is set to false is undefined behaviour. This is due to the output port not having a sign bit.

• The output_port_width must not be smaller than the input_port_width.

Testing

Tested platforms: None

Component testing not completed.