Equal To (`equal_to_ul_b`)

Test if the input sample is equal to a set value.

Design

Output a zero or one depending on if the signal is equal to the set value or not.

The mathematical representation of the implementation is given in (109).

(109)\[\begin{split}y[n] = \begin{cases} 1-i & x[n] == T \\ i & \text{otherwise} \end{cases}\end{split}\]

\(x[n]\) is the input values.

\(y[n]\) is the output values.

\(i\) is the invert_output property here considered as \(1\) for True and \(0\) for False.

\(T\) is the value the input data samples are compared to.

When invert_output is set to False the output will be one when the input is equal to the threshold, otherwise the output will be zero. When invert_output is set to True then the output will be zero when the input is equal to the threshold, otherwise the output will be one.

Interface

<?xml version="1.0"?>
<componentspec>
  <property name="value" type="ulong" writable="true" default="0" description="Value which the input data values are compared to."/>
  <property name="invert_output" type="bool" writable="true" default="0"
    description="When true the result of the comparison is inverted, before being output."/>
  <port name="input" producer="false" protocol="ulong_timed_sample-prot"/>
  <port name="output" producer="true" protocol="bool_timed_sample-prot"/>
</componentspec>

Ports

Inputs:

input: Primary input samples port.
- Protocol: ulong_timed_sample-prot
- Optional: False

Outputs:

output: Primary output samples port.
- Protocol: bool_timed_sample-prot
- Optional: False

Opcode Handling

Only values in a sample opcode message are compared to the set value. All other opcodes pass through this component without any effect.

Properties

value: Value which the input data values are compared to.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: 0
invert_output: When true the result of the comparison is inverted, before being output.
- Type: bool
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: 0

Implementations

equal_to_ul_b (HDL)
equal_to_ul_b (RCC)

Example Application

<?xml version="1.0"?>
<application done="file_write">
  <instance component="ocpi.core.file_read" connect="equal_to_ul_b">
    <property name="filename" value="input.bin"/>
  </instance>
  <instance component="ocpi.comp.sdr.logic.equal_to_ul_b" connect="file_write">
    <property name="va;ue" value="1000"/>
    <property name="invert_output" value="false"/>
  </instance>
  <instance component="ocpi.core.file_write">
    <property name="filename" value="output.bin"/>
  </instance>
</application>

Dependencies

The dependencies to other elements in OpenCPI are:

Protocol interface delay (wide to narrow) v2 primitive

There is also a dependency on:

ieee.std_logic_1164

ieee.numeric_std

Limitations

Limitations of equal_to_ul_b are:

None.

Testing

Tested platforms: None

Component testing not completed.

Equal To (equal_to_ul_b)